The Week In Review: Design

Barco Silex leaves Barco; DRC tools; EDA, IP revenue up.


Barco Silex, now named Silex Inside, split from parent company Barco in a management buyout in partnership with a group of private investors lead by Dutch investment company Vehold BV. The company will continue its focus on security, video compression, and interface IP, along with design services.

Tools & IP
Mentor is making a version of its HyperLynx design rule checking tool for PCBs available at no cost to PCB designers and hardware engineers. The tool includes eight design rules for automated signal integrity, power integrity, and EMI/EMC checks.

Aldec expanded the rule-checking capabilities of its ALINT-PRO DRC tool, adding rules to assure the integrity of a design’s Finite State Machines (FSMs) and help identify possible Reset Domain Crossing (RDC) issues.

Moortec has made its embedded process, voltage, and temperature monitoring subsystem available on TSMC’s 12nm FinFET Compact (FFC) process technology, enabling detection of process and manufacturing variation, DVFS optimization, and IR drop analysis. The subsystem includes a PVT Controller with AMBA APB interfacing.

Achronix completed full silicon verification of its Speedcore eFPGA production validation chip built on TSMC 16nm FinFET+ process technology.

Mentor updated its Nucleus RTOS process model to support asymmetric multiprocessing and symmetric multiprocessing on Arm 64-bit processors and multicore SoCs. The process model aims to increase system reliability by isolating faults to individual software subsystems, preventing other software subsystems from being impacted.

The EDA and IP sector continues to grow, with sales increasing 8% to $2.2262 billion in Q3, up from $2.0937 billion in the same period in 2016, according to the ESD Alliance Market Statistics Service. The four-quarter moving average was up 11.5%, year over year.

Japan in particular showed strong growth, with EDA revenue increasing 9.7% compared to last year with a four-quarter moving average. The country’s CAE revenue grew 15.2% over Q3 2016, while PCB/MCM was up 16.2%. “Japan is coming back again,” said Wally Rhines, board sponsor for ESD Alliance’s MSS and president and CEO of Mentor, a Siemens Business. He noted that employment in the region was up 9.9%: “That’s higher than the revenue growth rate for the industry. Companies are hiring additional people with the expectation of a strong growth market.” Compared to last quarter, employment across all regions is up 2%.

IP startup VSORA closed Series A financing with $1.7 million from venture capital firms Omnes Capital and Partech Ventures along with angel investors. Founded in 2015, the company focuses on DSPs targeting 5G communications. VSORA will use the funds to expand R&D and build sales channels in the United States and Asia.

Speech recognition startup Babblabs received $4 million in a Series Seed investment led by Cognite Ventures, with additional funding support from Jerry Yang of AME Cloud Ventures and independent investors John Hennessy, Harvey Jones, James Hogan and Kurt Keutzer. Chris Rowen, of Cognite, is CEO of Babblabs. The funds will be used for initial development and productization of cloud and embedded speech processing systems using deep neural network and audio processing technologies.

Startup incubator Silicon Catalyst and design services firm Intrinsix established an in-kind partnership to give Silicon Catalyst’s portfolio with access to chip designers and IP for digital, analog, RF and mixed-signal ICs.

Phil Kaufman Award Ceremony: Feb. 8 in San Jose, CA. Dr. Rob A. Rutenbar, senior vice chancellor for Research at the University of Pittsburgh, will be presented the 2017 Phil Kaufman Award for his contributions to algorithms and tools for analog and mixed-signal designs.

FPGA 2018: Feb. 25-27 in Monterey, CA. The conference includes a workshop on packet processing with the P4 language, a panel and several presentations focused on machine learning, and a look at new architectures.

DVCon 2018: Feb. 26-Mar. 1 in San Jose, CA. Features include tutorials on the Portable Stimulus Standard and UVM, a keynote on how new segments in the industry are changing verification, and a new slate of short workshops. Early registration ends next week.

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