The Week In Review: Design

By Jesse Allen - 19 Jan, 2018 - Comments: 0

M&A Barco Silex, now named Silex Inside, split from parent company Barco in a management buyout in partnership with a group of private investors lead by Dutch investment company Vehold BV. The company will continue its focus on security, video compression, and interface IP, along with design services. Tools & IP Mentor is making a version of its HyperLynx design rule checking tool ... » read more

The Week In Review: Design/IoT

By Jesse Allen - 13 May, 2016 - Comments: 0

Standards Si2 is launching a new project to develop a new power modeling standard, focusing on estimation of power consumption more easily and more accurately throughout the design process, especially during the earliest stages. The approved specification will be contributed to the IEEE P2416 Standards Working Group for industry-wide distribution. IP Synopsys extended automotive safety... » read more

The Week In Review: Design/IoT

By Jesse Allen - 10 Apr, 2015 - Comments: 0

Certifications TSMC certified a number of tools for its current 10nm FinFET design rules and SPICE models and 16nm FinFET Plus (16FF+) V1.0 process, including: Ansys' power integrity and electromigration tools; Cadence's custom/analog and digital implementation and signoff tools; Mentor Graphics' physical verification, design for manufacturing, and circuit verification tools; and Synopsys' ful... » read more

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Shift Left Is The Tip Of The Iceberg

A transformative change is underway for semiconductor design and EDA. New languages, models, and abstractions will need to be created.

by Brian Bailey

Partitioning In The Chiplet Era

Understanding how chiplets interact under different workloads is critical to ensuring signal integrity and optimal performance in heterogeneous designs.

by Ann Mutschler

NAND Flash Targets 1,000 Layers

New techniques go beyond improved deposition and etching, but challenges stack up, too.

by Bryon Moyer

3.5D: The Great Compromise

Pros and cons of a middle-ground chiplet assembly that combines 2.5D and 3D-IC.

by Ed Sperling

AI’s Role In Chip Design Widens, Drawing In New Startups

Focus is on letting engineers do much more with the same or fewer resources — and less drudgery.

by Karen Heyman

What Comes After HBM For Chiplets

The standard for high-bandwidth memory limits design freedom at many levels, but that is required for interoperability. What freedoms can be taken from other functions to make chiplets possible?

by Brian Bailey

Memory Fundamentals For Engineers

eBook: Nearly everything you need to know about memory, including detailed explanations of the different types of memory; how and where these are used today; what's changing, which memories are successful and which ones might be in the future; and the limitations of each memory type.

by The SE Staff

New AI Processors Architectures Balance Speed With Efficiency

Hot Chips 24: Large language models ratchet up pressure for sustainable computing and heterogeneous integration; data management becomes key differentiator.

by Ed Sperling

tag: Barco Silex

The Week In Review: Design

The Week In Review: Design/IoT

The Week In Review: Design/IoT

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