Enabling Advanced Devices With Atomic Layer Processes

By Katherine Derbyshire - 18 Apr, 2024 - Comments: 2

Atomic layer deposition (ALD) used to be considered too slow to be of practical use in semiconductor manufacturing, but it has emerged as a critical tool for both transistor and interconnect fabrication at the most advanced nodes. ALD can be speeded up somewhat, but the real shift is the rising value of precise composition and thickness control at the most advanced nodes, which makes the ext... » read more

Research Bits: July 11

By Jesse Allen - 11 Jul, 2022 - Comments: 0

Modeling ALE Scientists at U.S. Department of Energy’s (DOE) Princeton Plasma Physics Laboratory (PPPL), in coordination with Lam Research, modeled atomic layer etching (ALE) for semiconductor fabrication. “This would be one little piece in the whole process,” said David Graves, associate laboratory director for low-temperature plasma surface interactions at PPPL and a professor in th... » read more

Highly Selective Etch Rolls Out For Next-Gen Chips

By Mark LaPedus - 21 Mar, 2022 - Comments: 0

Several etch vendors are starting to ship next-generation selective etch tools, paving the way for new memory and logic devices. Applied Materials was the first vendor to ship a next-gen selective etch system, sometimes called highly-selective etch, in 2016. Now, Lam Research, TEL, and others are shipping tools with highly-selective etch capabilities, in preparation for futuristic devices su... » read more

Plasma processing for advanced microelectronics beyond CMOS

By Technical Paper Link - 27 Aug, 2021 - Comments: 0

N. Marchack, L. Buzi, D. B. Farmer, H. Miyazoe, J. M. Papalia, H. Yan, G. Totir, and S. U. Engelmann , "Plasma processing for advanced microelectronics beyond CMOS", Journal of Applied Physics 130, 080901 (2021) https://doi.org/10.1063/5.0053666 ABSTRACT "The scientific study of plasma discharges and their material interactions has been crucial to the development of semiconductor process en... » read more

MicroLEDs Moving From Lab to Fab

By Laura Peters - 22 Jul, 2021 - Comments: 1

Every disruptive technology has its "aha" moment — the time when everyone from engineers to investors realizes that, yes, this technology is the real deal and it won’t be scrapped on the R&D floor. For many, it was Samsung’s recent announcement of a 110-inch microLED TV that irrevocably put microLEDs on the map. The TV’s price is $155,000, but as with most consumer electronics th... » read more

Power Amp Wars Begin For 5G

By Mark LaPedus - 24 Aug, 2020 - Comments: 2

Demand is increasing for power amplifier chips and other RF devices for 5G base stations, setting the stage for a showdown among different companies and technologies. The power amplifier device is a key component that boosts the RF power signals in base stations. It's based on two competitive technologies, silicon-based LDMOS or RF gallium nitride (GaN). GaN, a III-V technology, outperforms ... » read more

Atomic Layer Etch Expands To New Markets

By Mark LaPedus - 16 Jul, 2020 - Comments: 0

The semiconductor industry is developing the next wave of applications for atomic layer etch (ALE), hoping to get a foothold in some new and emerging markets. ALE, a next-generation etch technology that removes materials at the atomic scale, is one of several tools used to process advanced devices in a fab. ALE moved into production for select applications around 2016, although the technolog... » read more

Challenges In Stacking, Shrinking And Inspecting Next-Gen Chips

By Ed Sperling and Mark LaPedus - 21 May, 2020 - Comments: 0

Rick Gottscho, CTO of Lam Research, sat down with Semiconductor Engineering to discuss memory and equipment scaling, new market demands, and changes in manufacturing being driven by cost, new technologies, and the application of machine learning. What follows are excerpts of that conversation. SE: We have a lot of different memory technologies coming to market. What's the impact of that? ... » read more

Making Chips At 3nm And Beyond

By Mark LaPedus and Ed Sperling - 16 Apr, 2020 - Comments: 4

Select foundries are beginning to ramp up their new 5nm processes with 3nm in R&D. The big question is what comes after that. Work is well underway for the 2nm node and beyond, but there are numerous challenges as well as some uncertainty on the horizon. There already are signs that the foundries have pushed out their 3nm production schedules by a few months due to various technical issu... » read more

Controlling Variability And Cost At 3nm And Beyond

By Ed Sperling - 22 May, 2019 - Comments: 1

Richard Gottscho, executive vice president and CTO of Lam Research, sat down with Semiconductor Engineering to talk about how to utilize more data from sensors in manufacturing equipment, the migration to new process nodes, and advancements in ALE and materials that could have a big impact on controlling costs. What follows are excerpts of that conversation. SE: As more sensors are added int... » read more

← Older posts

Knowledge Centers
Entities, people and technologies explored

Shift Left Is The Tip Of The Iceberg

A transformative change is underway for semiconductor design and EDA. New languages, models, and abstractions will need to be created.

by Brian Bailey

Partitioning In The Chiplet Era

Understanding how chiplets interact under different workloads is critical to ensuring signal integrity and optimal performance in heterogeneous designs.

by Ann Mutschler

3.5D: The Great Compromise

Pros and cons of a middle-ground chiplet assembly that combines 2.5D and 3D-IC.

by Ed Sperling

AI’s Role In Chip Design Widens, Drawing In New Startups

Focus is on letting engineers do much more with the same or fewer resources — and less drudgery.

by Karen Heyman

Key Technologies To Extend EUV To 14 Angstroms

Alongside high-NA EUV will be better-performing photoresists, reduced roughness using passivation and etch, and lateral etching to reduce tip-to-tip dimensions.

by Laura Peters

Memory Fundamentals For Engineers

eBook: Nearly everything you need to know about memory, including detailed explanations of the different types of memory; how and where these are used today; what's changing, which memories are successful and which ones might be in the future; and the limitations of each memory type.

by The SE Staff

What Comes After HBM For Chiplets

The standard for high-bandwidth memory limits design freedom at many levels, but that is required for interoperability. What freedoms can be taken from other functions to make chiplets possible?