Coherency Becomes A Stack Of Issues


By Ed Sperling As complexity increases and the industry increasingly shifts away from ASICs to SoCs, the concept of coherency is beginning to look more like a stack of issues than a discrete piece of the design. There are at least five levels of coherency that need to be considered already, with more likely to surface as stacked die become mainstream over the next few years. Perhaps even mo... » read more

Why PCs And Servers Aren’t Going Away


By Pallab Chatterjee With the rise of mobile appliances, smart phones and tablets, there has been a lot of discussion about the place for PCs, servers, embedded processors and networks. A number of companies have claimed they will rule the world of computing and there will no room for others. Reality seems to be somewhat different, however. The mobile end point devices—smart phones, table... » read more

Intel vs. AMD: Who’s Right?


By Barry Pangrle It’s all about the system. One energy-efficient component doesn’t an energy-efficient system make. There were two big announcements recently made by the industry’s two x86 designers. One was by Intel announcing its new Sandy Bridge Xeon Processor E5-2600 product family, and the other one was by AMD announcing its planned acquisition of SeaMicro. Both of these announce... » read more

Undervolting & Underclocking


By Barry Pangrle Last month we looked at record-breaking clock frequencies accompanied by voltage levels over 2V for some high-speed x86 processors. This month we’re going to go in the opposite direction—reducing the voltage and clock frequency to reduce power. Our processor of choice is the AMD A8-3850, a 100W, 2.9 GHz, quad-core, x86 processor that also incorporates 400 “Radeon core... » read more

Speed Demons


By Barry Pangrle For extreme world record performance levels, the required power levels are also typically extreme. It’s that age-old battle against diminishing returns to squeeze out every last drop of performance versus practical limits and wallets. For example, a top fuel dragster can consume about six gallons of fuel for a quarter-mile run down the strip. As has previously been shown ... » read more

Betting On Glass TSVs


By Ed Sperling There are two big issues when it comes to through-silicon vias. One involves cost. The second involves heat—in particular, how to get heat out of a stacked die and what the thermal coefficient of the TSV will be to make sure it expands at a rate consistent with the SoCs in a package. To address these issues, System-Level Design caught up with Rao Tummala, professor of elect... » read more

More Analog Needed For Multicore SoCs


By Mike Demler Minimizing on-chip power consumption continues to be one of the greatest challenges facing SoC designers. Everyone who owns a cell phone has undoubtedly seen the effect on limited battery life firsthand, but the impact on the unseen compute servers in “the cloud” is even more severe, making total electrical operating costs greater than the hardware expense, according to AMD ... » read more

The Big Picture


Business is booming for the makers of processors. Intel posted its five consecutive record quarter, AMD turned a profit, Tensilica shipped its billionth DSP, ARM and MIPS are both reporting strong earnings. So what’s changed? There are several distinct trends driving this upbeat mood: The replacement cycle. After years of putting off purchases through a prolonged and deep downturn, com... » read more

Tri-Gate’s Fallout


By David Lammers Intel Corp. dropped a rock into the pond of transistor technology when it announced its 22nm tri-gate technology in San Francisco earlier this month. The ripples continue to move out from that event, with impacts on IDMs, foundries, and fabless semiconductor companies being closely studied. Now that Intel has come out of the closet with its tri-gate technology, “the found... » read more

The Enterprise Effect


By Pallab Chatterjee In the enterprise it’s all about speed and power—as in more speed and less power—and those changes are forcing shifts in the chip architectures as well as the processes used to develop those chips. At the Linley Data Center Conference the next generation of network control chips were discussed. The keys for the new networks are 10G data lanes to be used with 10G/4... » read more

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