tag: analog

Post Layout Simulation Is Becoming The Bottleneck For Analog Verification
By Greg Curtis - 25 Jun, 2020 - Comments: 0

My, have times changed. I remember when I first started out as a green analog designer right out of college, we would cut rubylith masking film on a large light table representing the different layers of our design to generate the design for manufacturing of the chip. We proactively worked to mitigate cross coupling of noise to our signal nets, but we were rarely concerned about interconnect re... » read more

Aging Problems At 5nm And Below
By Brian Bailey - 11 Jun, 2020 - Comments: 3

The mechanisms that cause aging in semiconductors have been known for a long time, but the concept did not concern most people because the expected lifetime of parts was far longer than their intended deployment in the field. In a short period of time, all of that has changed. As device geometries have become smaller, the issue has become more significant. At 5nm, it becomes an essential par... » read more

Spiking Neural Networks: Research Projects or Commercial Products?
By Bryon Moyer - 18 May, 2020 - Comments: 2

Spiking neural networks (SNNs) often are touted as a way to get close to the power efficiency of the brain, but there is widespread confusion about what exactly that means. In fact, there is disagreement about how the brain actually works. Some SNN implementations are less brain-like than others. Depending on whom you talk to, SNNs are either a long way away or close to commercialization. Th... » read more

Layout Generators For Artificial Intelligence Hardware Design
By Benjamin Prautsch - 14 May, 2020 - Comments: 0

Artificial intelligence (AI) is a powerful tool that offers great convenience in many areas of life. In addition to improving Internet searches and online shopping, it enables driver assistance systems that can save lives, for example. AI in its various forms is the essential tool for such applications, and it can be expected to show a similar development as microelectronics did. Although AI... » read more

Low-Power Analog
By Brian Bailey - 14 May, 2020 - Comments: 3

Analog circuitry is usually a small part of a large SoC, but it does not scale in the same way as digital circuitry under Moore's Law. The power consumed by analog is becoming an increasing concern, especially for battery-operated devices. At the same time, little automation is available to help analog designers reduce consumption. "Newer consumer devices, like smartphones and wearables, alo... » read more

IC Test Solutions For The Automotive Market
By Mentor, a Siemens Business - 06 May, 2020 - Comments: 0

The amount of electronic content in passenger cars continues to grow rapidly, driven mainly by the integration of various advanced safety features, which will increase further with the move towards fully autonomous vehicles. It is critical that these safety-related devices adhere to the highest possible quality and reliability requirements formalized in the ISO 26262 standard that is being rapi... » read more

Improving Test Coverage And Eliminating Test Ecapes Using Analog Defect Analysis
By Cadence - 06 May, 2020 - Comments: 0

While the analog and mixed-signal components are the leading source of test escapes that result in field failures, the lack of tools to analyze the test coverage during design has made it difficult for designers to address the issue. In this white paper, we explore the methodology for performing analog fault simulation of test coverage based on defect-oriented testing. In addition, we look at h... » read more

Analog Design Needs To Change
By Dave Reed - 23 Apr, 2020 - Comments: 0

It’s an exciting time to be involved in analog design! Innovation in analog design methodology has been flourishing with the introduction of new tools and improved methodologies. And this innovation is badly needed; analog design is getting tougher. Design schedules remain tight, and the technical challenges analog designers face continue to grow – especially when moving to advanced node te... » read more

Building A Safety Verification Flow
By Ed Sperling - 24 Mar, 2020 - Comments: 0

Sal Alvarez, senior manager of application engineering at Synopsys, explains how safety verification differs from functional verification, what changes with failure mode effects analysis, and how to determine and verify the effectiveness of safety features. » read more

Memory Issues For AI Edge Chips
By Mark LaPedus - 23 Mar, 2020 - Comments: 3

Several companies are developing or ramping up AI chips for systems on the network edge, but vendors face a variety of challenges around process nodes and memory choices that can vary greatly from one application to the next. The network edge involves a class of products ranging from cars and drones to security cameras, smart speakers and even enterprise servers. All of these applications in... » read more

← Older posts Newer posts →

  • Sponsors

About

Navigation

Connect With Us

Copyright ©2013-2025 SMG   |  Terms of Service  |  Privacy Policy