tag: analog

Improving Design Collaboration In The Age Of Remote Work
By Amit Varde - 13 Sep, 2022 - Comments: 0

Teams of analog and mixed signal (AMS) design and layout engineers spend countless hours extracting every ounce of performance out of their design. They continually make incremental changes daily to the design until the very end, as close to tape out as possible. Each change made to the design requires corresponding changes to the circuit layout. As technology advances, accounting for the paras... » read more

A Multi-Level Analog IC Design Flow For Fast Performance Estimation Using Template-Based Layout Generators And Structural Models
By Fraunhofer IIS/EAS - 12 Sep, 2022 - Comments: 0

Analog IC design is a very challenging task as essential information is missing in the early design stages. Because the simulation of larger designs is exceedingly computationally expensive at lower abstraction levels, conservative assumptions are usually applied that often result in suboptimal performances such as area and power consumption. In order to enable both early performance estimates ... » read more

Verification Scorecard: How Well Is The Industry Doing?
By Brian Bailey - 25 Aug, 2022 - Comments: 0

Semiconductor Engineering sat down to discuss how well verification tools and methodologies have been keeping up with demand, with Larry Lapides, vice president of sales for Imperas Software; Mike Thompson, director of engineering for the verification task group at OpenHW; Paul Graykowski, technical marketing manager for Arteris IP; Shantanu Ganguly, vice president of product marketing at Caden... » read more

Novel In-Pixel-in-Memory (P2M) Paradigm for Edge Intelligence (USC)
By Technical Paper Link - 24 Aug, 2022 - Comments: 0

A new technical paper titled "A processing-in-pixel-in-memory paradigm for resource-constrained TinyML applications" was published by researchers at University of Southern California (USC). According to the paper, "we propose a novel Processing-in-Pixel-in-memory (P2M) paradigm, that customizes the pixel array by adding support for analog multi-channel, multi-bit convolution, batch normaliza... » read more

DNN-Opt, A Novel Deep Neural Network (DNN) Based Black-Box Optimization Framework For Analog Sizing
By Technical Paper Link - 19 Aug, 2022 - Comments: 0

This technical paper titled "DNN-Opt: An RL Inspired Optimization for Analog Circuit Sizing using Deep Neural Networks" is co-authored from researchers at The University of Texas at Austin, Intel, University of Glasgow. The paper was a best paper candidate at DAC 2021. "In this paper, we present DNN-Opt, a novel Deep Neural Network (DNN) based black-box optimization framework for analog sizi... » read more

Cloud-Ready Circuit Simulation Accelerates SoC Verification
By Nebabie Kebebew - 15 Aug, 2022 - Comments: 0

By Nebabie Kebebew and Nigel Bleasdale Driven by the explosion of big data and expanding applications, chip design complexity is increasing. Applications such as high-performance computing (HPC), the Internet of Things (IoT), automotive, and 5G mobile and communications coupled with advanced process technology nodes require running a large number of circuit simulations to ensure the circuits... » read more

Signoff-Accurate Partial Layout Extraction And Early Simulation
By Soni Kapoor - 11 Aug, 2022 - Comments: 0

It is a rewarding experience for EDA developers and users to collaborate on deploying advanced techniques to improve design productivity. This blog will describe the experience of collaborating with customers on a new technology for reducing the number of analog design iterations. Analog design requires that engineers balance the needs to 1) reach market quickly 2) deliver high quality 3) at lo... » read more

Analog Deep Learning Processor (MIT)
By Technical Paper Link - 29 Jul, 2022 - Comments: 0

A team of researchers at MIT are working on hardware for artificial intelligence that offers faster computing with less power. The analog deep learning technique involves sending protons through solids at extremely fast speeds.  “The working mechanism of the device is electrochemical insertion of the smallest ion, the proton, into an insulating oxide to modulate its electronic conductivity... » read more

The Reliability Of Analog Integrated Circuits And Their Simulation-Aided Verification
By Andre Lange - 19 Jul, 2022 - Comments: 0

Different challenges have to be overcome when designing integrated circuits. Besides schematic and layout design work, verification in view of the non-ideal behavior of circuits and semiconductor technologies in particular is also relevant. The designed circuits have to work at specific operating voltages and within ambient temperature ranges and be robust in terms of process fluctuations ... » read more

IC Reliability Burden Shifts Left
By Ann Mutschler - 23 Jun, 2022 - Comments: 0

Chip reliability is coming under much tighter scrutiny as IC-driven systems take on increasingly critical and complex roles. So whether it's a stray alpha particle that flips a memory bit, or some long-dormant software bugs or latent hardware defects that suddenly cause problems, it's now up to the chip industry to prevent these problems in the first place, and solve them when they do arise. ... » read more

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