tag: ANSYS

Differential Energy Analysis To Optimize Mobile GPU Power
By Ansys - 15 Jul, 2019 - Comments: 0

Operating power has become one of the most important metrics for modern electronic devices. Qualcomm Technologies, a world-class mobile solution provider, significantly reduced power consumption in an already challenging market by performing power analysis at RTL using ANSYS PowerArtist. Qualcomm Technologies was able to reduce dynamic power by 10 percent through this approach. To read more,... » read more

Blog Review: July 10
By Jesse Allen - 10 Jul, 2019 - Comments: 0

Synopsys' Eric Huang takes a look at how backward compatibility with USB 2.0 is provided when the IO voltages of new nodes can't support 3.3V signaling and how eUSB2 can boost the signal and provide support for external or legacy peripherals. In a video, Mentor Colin Walls explains endianness in embedded systems with a look at what it is, when it matters, and how to accommodate it in code. ... » read more

Silicon Photonics Begins To Make Inroads
By Kevin Fogarty and Ed Sperling - 09 Jul, 2019 - Comments: 1

Integrating photons and electrons on the same die is still a long way off, but advances in packaging and improvements in silicon photonics are making it possible to use optical communication for a variety of new applications. Utilizing light-based communication between chips, or in self-contained modules, ultimately could have a big impact on chip design. Photons moving through waveguides ar... » read more

HW/SW Design At The Intelligent Edge
By Ann Mutschler - 08 Jul, 2019 - Comments: 0

Adding intelligence to the edge is a lot more difficult than it might first appear, because it requires an understanding of what gets processed where based on assumptions about what the edge actually will look like over time. What exactly falls under the heading of Intelligent Edge varies from one person to the next, but all agree it goes well beyond yesterday’s simple sensor-based IoT dev... » read more

Security’s Very Strange Path To Success
By Ed Sperling - 02 Jul, 2019 - Comments: 0

Security at the chip level appears to be heading toward a more promising future. The reason is simple—more people are willing to pay for security than in the past. For the most part, security is like insurance. You don't know it's working until something goes wrong, and you don't necessarily even know right away if there has been a breach. Sometimes it takes years to show up, because it ca... » read more

Week In Review: Design, Low Power
By Jesse Allen - 28 Jun, 2019 - Comments: 0

VESA published the DisplayPort 2.0 standard, which allows for a max payload of 77.37 Gbps, a 3X increase in data bandwidth performance compared to DisplayPort 1.4a. The latest release also includes capabilities to address beyond 8K resolutions, higher refresh rates and HDR support at higher resolutions, multiple display configurations, and support for 4K-and-beyond VR resolutions. It is backwar... » read more

Blog Review: June 26
By Jesse Allen - 26 Jun, 2019 - Comments: 0

Arm's Krish Nathella and Dam Sunwoo dig into research to make a practical implementation of a temporal data prefetcher that overcomes the huge on- and off-chip storage and traffic overheads usually associated with them. Cadence's Paul McLellan notes that while concerns about uncover bias in computer vision algorithms usually focus on people, a team at Facebook found that object recognition t... » read more

Week In Review: Design, Low Power
By Jesse Allen - 21 Jun, 2019 - Comments: 0

ON Semiconductor completed its $946 million acquisition of Quantenna Communications, a San Jose-based company that specializes in Wi-Fi chips and software. Aldec introduced automatic UVM register generation to its Riviera-PRO verification platform. Riviera-PRO can now accept a CSV file or IP-XACT register description as an input and, working at the Register Abstraction Layer (RAL) of UVM, ou... » read more

Wrestling With High-Speed SerDes
By Ann Mutschler - 19 Jun, 2019 - Comments: 2

SerDes has emerged as the primary solution in chips where there is a need for fast data movement and limited I/O, but this technology is becoming significantly more challenging to work with as speeds continue to rise to offset the massive increase in data. A Serializer/Deserializer is used to convert parallel data into serial data, allowing designers to speed up data communication without h... » read more

Power, Reliability And Security In Packaging
By Ed Sperling - 19 Jun, 2019 - Comments: 0

Semiconductor Engineering sat down to discuss advanced packaging with Ajay Lalwani, vice president of global manufacturing operations at eSilicon; Vic Kulkarni, vice president and chief strategist in the office of the CTO at ANSYS; Calvin Cheung, vice president of engineering at ASE; Walter Ng, vice president of business management at UMC; and Tien Shiah, senior manager for memory at Samsun... » read more

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