IP Becoming More Complex, More Costly


Success in the semiconductor intellectual property (IP) market requires more than a good bit of RTL. New advances mandate a complete design, implementation, and verification team, which limits the number of companies competing in this market. What constitutes an IP block has changed significantly since the concept was first introduced in the 1990s. What was initially just a piece of RTL (reg... » read more

Blog Review: May 24


Siemens' Patrick McGoff finds that designers have not had easy tools to address solderability, leaving a critical part of the manufacturing success of a PCB to the component engineer or the contract manufacturer, and points to manufacturing-driven design as a way to avoid quality issues later. Cadence's Rich Chang finds that effective UPF low-power verification and debug involves more than o... » read more

Week In Review: Design, Low Power


Design Ansys has signed a definitive agreement to acquire EDA tool company Diakopto. Diakopto specializes in software tools that find the cause of layout parasitics. Its products are ParagonX, for analyzing and debugging IC designs and layout parasitics, and EM/IR analysis/verification tool PrimeX. The deal is expected to close in the second quarter of 2023. SEMI’s FlexTech community issu... » read more

Blog Review: May 17


Synopsys' Dana Neustadter examines the key industries driving Ethernet security, challenges to securing Ethernet networks, and the MACsec protocol that guards against network data breaches by encrypting data traffic between Ethernet-connected devices. Siemens' Stephen Chavez points to the improvements gained from design reuse in PCB design but warns that inefficient processes for managing an... » read more

Holistic Power Reduction


The power consumption of a device is influenced by every stage of the design, development, and implementation process, but identifying opportunities to save power no longer can be just about making hardware more efficient. Tools and methodologies are in place for most of the power-saving opportunities, from RTL down through implementation, and portions of the semiconductor industry already a... » read more

3D-IC Design: An Innovative Approach To Chip Integration


Advancements in technology have led to the development of increasingly complex and densely integrated circuits (ICs). To keep up with the ever-growing demand for high-performance and power-efficient devices, the industry has shifted toward 3D-IC design. 3D-ICs have many applications in a wide range of industries, including consumer electronics, telecommunications, computing, and automotive. Wh... » read more

Engineering Simulation Workloads And The Rise of the Cloud


Cloud service providers (CSPs) continue to improve the performance capabilities of their non-accelerated and accelerated compute instances, as well as augment their HPC infrastructure with domain-area expertise of targeted HPC workloads. Additionally, engineers, researchers, and scientists are becoming more comfortable with the types of workloads that can be run in the cloud within acceptable w... » read more

Blog Review: May 10


Synopsys' Alessandra Nardi and Uyen Tran explain how to meet quality, reliability, functional safety, and security requirements of automotive chips through thorough test programs, path-margin monitoring, and design failure mode and effect analysis (DFMEA). Cadence's Veena Parthan explores how computational fluid dynamics can help predict and model the generation, propagation, and mitigation ... » read more

Week In Review: Semiconductor Manufacturing, Test


The global sales slump in semiconductors but may be stabilizing, according to a new report from the Semiconductor Industry Association (SIA). Worldwide sales of semiconductors fell 8.7% in Q1 2023 compared to the Q4 2022, and dropped 21.3% compared to the Q1 2022. Sales for the month of March 2023 increased 0.3% compared to February 2023. Meanwhile, SEMI reports worldwide silicon wafer shipment... » read more

Blog Review: May 3


Synopsys' Thomas Andersen considers the requirements of AI-optimized chips that are resulting in exploration of different memory configurations, different types of memory, and different types of processor technologies and software components. Cadence's Girish Vaidyanathan considers the role of hierarchy and partitioning in custom design and looks at how a virtual hierarchy allows layout desi... » read more

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