tag: ANSYS

True 3D-IC Problems
By Brian Bailey - 27 Apr, 2023 - Comments: 0

Placing logic on logic may sound like a small step, but several problems must be overcome to make it a reality. True 3D involves wafers stacked on top of each other in a highly integrated manner. This is very different from 2.5D integration, where logic is placed side-by-side, connected by an interposer. And there are some intermediate solutions today where significant memory is stacked on l... » read more

Blog Review: April 26
By Jesse Allen - 26 Apr, 2023 - Comments: 0

Codasip's Tora Fridholm introduces the NimbleAI project, an effort to design a neuromorphic sensing and processing 3D integrated chip that implements an always-on sensing stage, highly specialized event-driven processing kernels and neural networks to perform visual inference of selected stimuli using the bare minimum amount of energy. Synopsys' Anjaneya Thakar discusses computational lithog... » read more

Week In Review: Design, Low Power
By Linda Christensen - 21 Apr, 2023 - Comments: 0

Cadence rolled out a slew of new products at this week’s CDNLive Silicon Valley, including: A new generative AI-powered tool for analog, mixed-signal, RF and photonics design; An extended collaboration with TSMC and Microsoft to advance giga-scale physical verification system in the cloud; A multi-year partnership with the San Francisco 49ers football organization, focused on sust... » read more

Week In Review: Auto, Security, Pervasive Computing
By SE Staff - 21 Apr, 2023 - Comments: 0

Pervasive computing Broadcom announced delivery of its Jericho3-AI fabric for artificial intelligence (AI) networks, which delivers 26 petabits per second of Ethernet bandwidth. That is roughly four times the bandwidth of the previous generation, at a 40% power savings per gigabit. AMD released the Ryzen Embedded 5000 Series processors for customers requiring power-efficient processors opt... » read more

Blog Review: April 19
By Jesse Allen - 19 Apr, 2023 - Comments: 0

Synopsys' Soren Smidstrup and Kerim Genc explore how materials modeling helps battery designers explore the wide playing field for new battery materials and optimize performance by co-designing the structure and chemistry of new batteries, ultimately shortening development time and cost. Siemens' Stephen Chavez finds that enabling multiple engineers to work simultaneously within the same PCB... » read more

Week In Review: Design, Low Power
By Jesse Allen - 14 Apr, 2023 - Comments: 0

Arm and Intel Foundry Services inked a multi-generation agreement to enable chip designers to build Arm-based SoCs on the Intel 18A process. The initial focus is mobile SoC designs, but the deal allows for potential expansion into automotive, IoT, data center, aerospace, and government applications. IFS and Arm will undertake design technology co-optimization (DTCO) to optimize chip design and ... » read more

Week In Review: Auto, Security, Pervasive Computing
By SE Staff - 14 Apr, 2023 - Comments: 0

Public USB phone charging stations are now another vector that bad actors can use to plant malware and steal data on devices — known as "juice jacking," according to the United States’ Federal Communications Commission (FCC). The FCC is encouraging people to stay away from these public charging stations, found in airports and hotels, because of bad actors can install malware on the charging... » read more

Thermal Integrity Challenges Grow In 2.5D
By Ann Mutschler - 13 Apr, 2023 - Comments: 3

Thermal integrity is becoming much harder to predict accurately in 2.5D and 3D-IC, creating a cascade of issues that can affect everything from how a system behaves to reliability in the field. Over the past decade, silicon interposer technology has evolved from a simple interconnect into a critical enabler for heterogeneous integration. Interposers today may contain tens of dies or chiplets... » read more

What Designers Need To Know About GAA
By Brian Bailey - 13 Apr, 2023 - Comments: 3

While only 12 years old, finFETs are reaching the end of the line. They are being supplanted by gate-all-around (GAA), starting at 3nm [1], which is expected to have a significant impact on how chips are designed. GAAs come in two main flavors today — nanosheets and nanowires. There is much confusion about nanosheets, and the difference between nanosheets and nanowires. The industry still ... » read more

How To Plan And Conduct Highly Accelerated Life Testing
By Chris South - 13 Apr, 2023 - Comments: 0

Assessing the robustness of an electronic product is integral to successful design and performance. Highly accelerated life testing (HALT) is an important testing tool for this purpose, and its effectiveness can be maximized through careful planning prior to setup and detailed execution. What is HALT? HALT is the process of applying increased stressors to an electronic device to force failure... » read more

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