Blog Review: Sept. 29

By Jesse Allen - 29 Sep, 2021 - Comments: 0

Cadence's Paul McLellan checks out two of the biggest chips presented at the recent Hot Chips: a graphics chip from Intel for an upcoming supercomputer and Cerebras' wafer-scale AI chip. Synopsys' Datsen Davies Tharakan lists the top five design challenges for electric vehicles and power semiconductors and why a robust design flow can accelerate the growth of hybrid and electric vehicles goi... » read more

Building Complex Chips That Last Longer

By Ed Sperling - 23 Sep, 2021 - Comments: 0

Semiconductor Engineering sat down to talk about design challenges in advanced packages and nodes with John Lee, vice president and general manager for semiconductors at Ansys; Shankar Krishnamoorthy, general manager of Synopsys' Design Group; Simon Burke, distinguished engineer at Xilinx; and Andrew Kahng, professor of CSE and ECE at UC San Diego. This discussion was held at the Ansys IDEAS co... » read more

Blog Review: Sept. 22

By Jesse Allen - 22 Sep, 2021 - Comments: 0

Ansys' Tyler Ferris describes some of the many ways electronics on a PCB assembly can fail, from component level failures like wirebond breaking and liftoff to board-level failures such as conductive anodic filament failure. Cadence's Paul McLellan considers the switch from low-speed parallel interfaces to high-speed serial interfaces as one of the key advancements making modern data centers... » read more

Week In Review: Design, Low Power

By Jesse Allen - 17 Sep, 2021 - Comments: 0

MoSys, a provider of SRAM solutions and networking accelerators, and Peraso Technologies, a provider of 5G mmWave devices, are merging. Stockholders of Peraso are expected to hold a 61% equity interest in the combined company, with the remaining 39% equity interest to be retained by the stockholders of MoSys. Peraso CEO Ronald Glibbery said, "By joining with MoSys, we believe we can deliver a b... » read more

Week In Review: Auto, Security, Pervasive Computing

By Susan Rambo - 17 Sep, 2021 - Comments: 0

Automotive Arm announced a new software architecture, two reference hardware implementations, and its role leading a new industry group that will work on open-source software for automotive use. The Scalable Open Architecture for Embedded Edge (SOAFEE) is based on Arm’s Project Cassini and SystemReady, aims to help the automotive industry move to software-defined systems by tackling the comp... » read more

Blog Review: Sept. 15

By Jesse Allen - 15 Sep, 2021 - Comments: 0

Synopsys' Ian Land and Ricardo Borges examine how radiation modeling can help ensure semiconductor components will survive while housed in equipment that is orbiting our planet or traveling through deep space over extensive periods of time. Siemens EDA's Rich Edelman explores why writing coverage is an art requiring imagination, practice, and patience, along with some tips on how to improve.... » read more

Week In Review: Auto, Security, Pervasive Computing

By Susan Rambo - 10 Sep, 2021 - Comments: 0

Automotive Intel’s Mobileye and Sixt SE said they are collaborating on an autonomous ride-hailing services in Munich in 2022. Mobileye will own the robotaxi fleet. Mobileye also recently unveiled its electric autonomous vehicle (AV), which it will use in ridehailing in Munich and Tel Aviv.. To increase the supply of automotive chips, Intel said it will build new chip manufacturing facilit... » read more

The Impact Of Multiphysics On Production Electronic Design

By Marc Swinnen - 09 Sep, 2021 - Comments: 0

For many electronic design professionals, it has become clear that the industry is transitioning through an inflection point that is shifting some of the ground rules of design. The increase in the speed and integration density in today’s systems are blurring the lines between chip design and traditional board or system design. This finds its fullest expression in multi-die, 3D integrated ... » read more

Blog Review: Sept. 8

By Jesse Allen - 08 Sep, 2021 - Comments: 0

Synopsys' Scott Durrant considers the IP used in HPC SoCs and the efforts to simultaneously minimize data movement and maximize the speed at which data is transferred from one location to another, whether that data transfer is across long distances or from one chip to another within a server. Cadence's Paul McLellan looks into a new version of the Rowhammer DRAM vulnerability that can allow ... » read more

Edge Computing: New Support For Digital Twins

By Ansys - 08 Sep, 2021 - Comments: 0

Digital twins are one of the most exciting technology developments to emerge over the past few years. By creating a virtual model of a physical product, then simulating its real-time operation, companies are optimizing maintenance, predicting critical maintenance events and fueling innovation via actual performance feedback. Because simulation requires computational resources and the associated... » read more

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Knowledge Centers
Entities, people and technologies explored

Shift Left Is The Tip Of The Iceberg

A transformative change is underway for semiconductor design and EDA. New languages, models, and abstractions will need to be created.

by Brian Bailey

Partitioning In The Chiplet Era

Understanding how chiplets interact under different workloads is critical to ensuring signal integrity and optimal performance in heterogeneous designs.

by Ann Mutschler

3.5D: The Great Compromise

Pros and cons of a middle-ground chiplet assembly that combines 2.5D and 3D-IC.

by Ed Sperling

Legacy Process Nodes Going Strong

The critical, and growing, significance of mature node chips and processes.

by Bryon Moyer

AI’s Role In Chip Design Widens, Drawing In New Startups

Focus is on letting engineers do much more with the same or fewer resources — and less drudgery.

by Karen Heyman

Key Technologies To Extend EUV To 14 Angstroms

Alongside high-NA EUV will be better-performing photoresists, reduced roughness using passivation and etch, and lateral etching to reduce tip-to-tip dimensions.

by Laura Peters

Memory Fundamentals For Engineers

eBook: Nearly everything you need to know about memory, including detailed explanations of the different types of memory; how and where these are used today; what's changing, which memories are successful and which ones might be in the future; and the limitations of each memory type.

by The SE Staff

What Comes After HBM For Chiplets

The standard for high-bandwidth memory limits design freedom at many levels, but that is required for interoperability. What freedoms can be taken from other functions to make chiplets possible?

by Brian Bailey

tag: ANSYS

Blog Review: Sept. 29

Building Complex Chips That Last Longer

Blog Review: Sept. 22

Week In Review: Design, Low Power

Week In Review: Auto, Security, Pervasive Computing

Blog Review: Sept. 15

Week In Review: Auto, Security, Pervasive Computing

The Impact Of Multiphysics On Production Electronic Design

Blog Review: Sept. 8

Edge Computing: New Support For Digital Twins