tag: ANSYS

Blog Review: Dec. 11
By Jesse Allen - 11 Dec, 2019 - Comments: 0

Arm's Urmish Thakker investigates ways to make recurrent neural networks run on resource constrained devices with limited cache and compute resources by reducing the number of RNN computations, without the need to retrain the original RNN model. Mentor's Brent Klingforth digs into the challenges of designing rigid-flex PCBs and how advanced capabilities in modern tools, like awareness of sta... » read more

Three Levers for Accelerating Lightweighting in Aerospace: Advanced Materials, Additive Manufacturing, Materials Intelligence
By Ansys - 11 Dec, 2019 - Comments: 0

Accelerating the delivery of lighter weight aircraft is possible by focusing on three key levers: more extensive use of advanced materials, broader adoption of new manufacturing techniques and extraction of more value from existing materials data. This white paper delves into the opportunities and challenges presented by each, and provides best practices for reducing fuel costs and emissions th... » read more

Week In Review: IoT, Security, Auto
By SE Staff - 06 Dec, 2019 - Comments: 0

Internet of Things SiFive is bringing RISC-V to IoT makers and university developers through the RISC-V-based SiFive Learn Initiative, an open-source learning package that can be used to create a low-cost RISC-V hardware compatible with AWS IoT Core. The development platform SiFive Learn Inventor has a software package and education enablement course. It includes: The programmable SiFive Lear... » read more

Blog Review: Dec. 4
By Jesse Allen - 04 Dec, 2019 - Comments: 0

Arm's Rupal Gandhi digs into the Cell-Aware Test methodology to deterministically target the growing number of defects that occur within the cells, the process of CAT library generation, and compares the static and transition patterns generated. Cadence's Paul McLellan shares highlights from the recent WOSET event with a look at the big drivers for the current interest in open-source EDA too... » read more

Blog Review: Nov. 27
By Jesse Allen - 27 Nov, 2019 - Comments: 0

Arm's Ben Fletcher digs into what's needed to make wireless 3D integration a reality from a tool to automate the design and optimization process for inductors used in wireless 3D-ICs to exploring how the data can be encoded in the transceiver to reduce power consumption. Cadence's Paul McLellan listens in as Eli Singerman of Intel explains the importance of platform security and why firmware... » read more

Electromagnetic Challenges In High-Speed Designs
By Ed Sperling - 25 Nov, 2019 - Comments: 0

ANSYS’ Anand Raman, senior director, and Nermin Selimovic, product sales specialist, talk with Semiconductor Engineering about how to deal with rising complexity and tighter tolerances in AI, 5G, high-speed SerDes and other chips developed at the latest process nodes where the emphasis is on high performance and low power. » read more

Week In Review: Design, Low Power
By Jesse Allen - 22 Nov, 2019 - Comments: 1

Accellera formed the Universal Verification Methodology Analog/Mixed-Signal Working Group (UVM-AMS WG), which will work to develop a standard that will provide a unified analog/mixed-signal verification methodology based on UVM to improve the verification of AMS integrated circuits and systems. “Our objective is to standardize a method to drive and monitor analog/mixed-signal nets within UVM,... » read more

Week In Review: IoT, Security, Automotive
By SE Staff - 22 Nov, 2019 - Comments: 0

Automotive Porsche’s electric race car, the 99X Electric, used ANSYS Technology’s system-level simulation solutions to create an advanced electric powertrain. The powertrain is also being adapted for use in Porsche’s consumer electric cars. "ANSYS system-level simulations are instrumental for optimizing the Porsche E-Performance Powertrain's motor, gearbox, power electronics and control ... » read more

Blog Review: Nov. 20
By Jesse Allen - 20 Nov, 2019 - Comments: 0

Arm's Ben Fletcher points to research into a new low-cost alternative to through-silicon vias in 3D stacked ICs, particularly cost-sensitive IoT designs, where communication between silicon layers is completely wireless. Cadence's Paul McLellan checks in on the progress of DARPA's OpenROAD project to build a no-human-in-the-loop open source EDA flow for leading-edge nodes. Mentor's Colin ... » read more

The Challenge Of Defining Worst Case
By Brian Bailey - 14 Nov, 2019 - Comments: 0

Worst case conditions within a chip are impossible to define. But what happens if you missed a corner case that causes chip failure? As the semiconductor market becomes increasingly competitive — startups and systems companies are now competing with established chipmakers — no one can afford to consider theoretical worst cases. Instead, they must intelligently prune the space to make sur... » read more

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