tag: ANSYS

Open-Source Verification
By Brian Bailey - 30 Jul, 2020 - Comments: 1

Ask different people what open-source verification means and you will get a host of different answers. They range from the verification of open-source hardware, to providing an open-source verification infrastructure, to providing open-source stream generators or reference models, to open-source simulators and formal verification engines. Verification is about reducing risk. "Verification is... » read more

Blog Review: July 29
By Jesse Allen - 29 Jul, 2020 - Comments: 0

Rambus' Scott Best digs into low-cost attacks against security chips that are often used to gauge how resistant and well-designed they are and defensive countermeasures that can be taken. Mentor's Colin Walls urges embedded developers to put a priority on writing clear, maintainable code and considers when using a higher level language like C++ may be helpful. Synopsys' Scott Knowlton fin... » read more

Week In Review: Design, Low Power
By Jesse Allen - 24 Jul, 2020 - Comments: 0

Perforce Software acquired Methodics. Founded in 2006 and based in San Francisco, Methodics' IP lifecycle management and traceability software will join Perforce's larger portfolio of DevOps software that includes version control, Agile planning, and static code analysis. The two companies have had a strategic partnership in place with customers using software from both companies. Terms of the ... » read more

EDA On Board With New Package Options
By Ann Mutschler - 22 Jul, 2020 - Comments: 2

A groundswell of activity around multi-die integration and advanced packaging is pushing EDA companies to develop integration strategies that speed up time to sign-off, increase confidence that a design will work as expected, while still leaving enough room for highly customized solutions. Challenges range from how to architect a design, how to explore the best options and configurations, ho... » read more

Blog Review: July 22
By Jesse Allen - 22 Jul, 2020 - Comments: 0

In a video, Synopsys Chairman and co-CEO Aart de Geus discusses AI's computational wants, how 3DIC technology can infuse vitality into Moore’s Law and drive innovation for the semiconductor industry. Cadence's Paul McLellan looks back at the initial rise of digital cameras, the swift decline of the point-and-shoot as smartphones took over, and the development of increasingly complex CMOS i... » read more

Week In Review: Design, Low Power
By Jesse Allen - 17 Jul, 2020 - Comments: 0

Siemens will acquire Avatar Integrated Systems. The company's place-and-route tools, which will become part of Mentor's Xcelerator portfolio, include a netlist-to-GDS full-function block-level physical implementation tool and a complete top-level prototyping, floor-planning and chip assembly tool. Based in Santa Clara, CA, Avatar was formed in 2017 from the acquired assets of ATopTech. ATopTech... » read more

Smaller Nodes, Much Bigger Problems
By Ed Sperling - 15 Jul, 2020 - Comments: 3

João Geada, chief technologist at Ansys, sat down with Semiconductor Engineering to talk about device scaling, advanced packaging, increasing complexity and the growing role of AI. What follows are excerpts of that conversation. SE: We've been pushing along Moore's Law for roughly a half-century. What sorts of problems are you seeing now that you didn't see a couple nodes ago? Geada: The... » read more

Blog Review: July 15
By Jesse Allen - 15 Jul, 2020 - Comments: 0

Synopsys' Mike Borza explains DARPA's Automatic Implementation of Secure Silicon (AISS) program and why prioritizing security in the chip development and manufacturing process is so important. Mentor's Jacob Wiltgen checks out how accurate early cycle safety analysis, aided by automation, can help avoid the problem of unmet safety goals and expensive later cycle iterations. Cadence's Paul... » read more

Designing For Extreme Low Power
By Brian Bailey - 09 Jul, 2020 - Comments: 3

There are several techniques available for low power design, but whenever a nanowatt or picojoule matters, all available methods must be used. Some of the necessary techniques are different from those used for high-end designs. Others have been lost over time because their impact was considered too small, or not worth the additional design effort. But for devices that last a lifetime on a si... » read more

Power Impact At The Physical Layer Causes Downstream Effects
By Ann Mutschler - 09 Jul, 2020 - Comments: 0

Data movement is rapidly emerging as one of the top design challenges, and it is being complicated by new chip architectures and physical effects caused by increasing density at advanced nodes and in multi-chip systems. Until the introduction of the latest revs of high-bandwidth memory, as well as GDDR6, memory was considered the next big bottleneck. But other compute bottlenecks have been e... » read more

← Older posts Newer posts →

  • Sponsors

About

Navigation

Connect With Us

Copyright ©2013-2026 SMG   |  Terms of Service  |  Privacy Policy