tag: Apache Design Solutions

Thermal Modeling Held Back By Outdated Standards
By Ed Sperling - 06 Oct, 2011 - Comments: 0

By Ann Steffora Mutschler As the reality of true 3D IC design nears, engineering teams are keen to manage the heat between the stacked die in order to avoid catastrophic failures. Thermal modeling tops the roster of techniques to leverage in this area. Herve Jaouen, director of modeling and simulation in STMicroelectronics’ technology R&D organization, explained that in 3D designs the... » read more

Power and Noise Integrity for Analog/Mixed-Signal Designs
By Various Writers - 06 Oct, 2011 - Comments: 0

This paper describes the need for power noise integrity solution for analog / mixed-signal designs and the benefits of the Totem platform, its usage model in a design flow, and results from simulation and correlation measurements. To download this paper, click here. » read more

Picking The Right Models
By Various Writers - 08 Sep, 2011 - Comments: 0

By Ji Zheng As the focus on “efficient computing” increases and ICs are fabricated using process technologies that are more sensitive to voltage fluctuations, accurate modeling and prediction of chip-level, package-level and system-level behavior becomes a necessary design step. The use of chip macro models enables 3D-IC and IC-package-PCB co-analysis for power integrity, signal integrity,... » read more

Heat Wreaks Havoc
By Ed Sperling - 08 Sep, 2011 - Comments: 0

By Ann Steffora Mutschler As semiconductor manufacturing technology has scaled ever smaller, the density of power grid networks has caused on-chip temperatures to rise, negatively impacting performance, power, and reliability. CMOS technology, still the predominant material in SoCs, was originally conceived as a low-power technology when compared with the bipolar approach, which was a very... » read more

New Stacking Issues
By Norman Chang - 11 Aug, 2011 - Comments: 0

Reduced form factors, higher performance, and the demand for lower power necessitate the need for 3D-IC/silicon interposer designs with through-silicon vias (TSVs). That also creates major design challenges in three areas. The verification of power, signal, and reliability integrity—particularly with multi-stacked die on silicon interposer with TSVs—presents issues that can only be overcome... » read more

Apache Update: Five Important Questions
By Ed Sperling - 11 Aug, 2011 - Comments: 0

By Ed Sperling It was supposed to be the first IPO since Magma went public in 2001. Instead, Apache was bought by Ansys in a deal that closed earlier this month—at a record pace for the EDA industry of less than two months since it was announced. So what exactly was behind the acquisition and why did Apache agree to sell? And what will become of Apache within the much larger Ansys? Low... » read more

Design For Power Methodology
By Ed Sperling - 21 Jul, 2011 - Comments: 0

By Ann Steffora Mutschler It is rare to find an advanced chip today that has not been designed considering power from the very earliest point. In fact, it is safe to say that power is the No. 1 priority, or a close No. 2. But to achieve the highest performance for a low-power design, a design-for-power methodology is necessary, comprised of the capabilities to implement power in the most ef... » read more

Top 5 Reasons For Power Consumption Waste
By William Ruby - 21 Jul, 2011 - Comments: 0

By William Ruby Low-power seems to be on everyone’s mind these days, and it’s not just the chip design teams. One common consumer complaint is that the “battery life is way too short”! And of course, we all know this one, “OMG – that laptop is sure hot“! Even data center facilities managers lament, “We can’t supply enough power to the equipment—and when we do, we can’t co... » read more

RTL Design For Power Methodology
By Various Writers - 21 Jul, 2011 - Comments: 0

This power budgeting white paper presents a design-for-power methodology, starting early in the design process at the Register Transfer Level (RTL), to help deliver maximum impact on power. To download this white paper, click here. » read more

Going With The Flow
By Ed Sperling - 15 Jul, 2011 - Comments: 0

It’s hard to judge things in isolation, but a continuum of acquisitions in the low-power area is proving just how important power considerations have become to hardware and software design, verification and manufacturing flows. Over the past couple of years acquisitions by Synopsys in the virtual prototyping arena, and Mentor Graphics in the test and embedded software area, have included p... » read more

← Older posts Newer posts →

  • Sponsors

About

Navigation

Connect With Us

Copyright ©2013-2024 SMG   |  Terms of Service  |  Privacy Policy