Photomask Shortages Grow At Mature Nodes


A surge in demand for chips at mature nodes, coupled with aging photomask-making equipment at those geometries, are causing significant concern across the supply chain. These issues began to surface only recently, but they are particularly worrisome for photomasks, which are critical for chip production. Manufacturing capacity is especially tight for photomasks at 28nm and above, driving up ... » read more

Blog Review: April 20


Cadence's Paul McLellan looks at the difference between 3D packaging and 3D integration and the different approaches to system-in-package designs. Siemens' Spencer Acain finds that despite having less precision and flexibility than digital chips, analog computing is having a resurgence in the space of cutting-edge AI thanks to the speed and energy efficiency in specialized tasks. Synopsys... » read more

Strategies For Faster Yield Ramps On 5nm Chips


Leading chipmakers TSMC and Samsung are producing 5nm devices in high volume production and TSMC is forging ahead with plans for first 3nm silicon by year end. But to meet such aggressive targets, engineers must identify defects and ramp yield faster than before. Getting a handle on EUV stochastic defects — non-repeating patterning defects such as microbridges, broken lines, or missing con... » read more

Highly Selective Etch Rolls Out For Next-Gen Chips


Several etch vendors are starting to ship next-generation selective etch tools, paving the way for new memory and logic devices. Applied Materials was the first vendor to ship a next-gen selective etch system, sometimes called highly-selective etch, in 2016. Now, Lam Research, TEL, and others are shipping tools with highly-selective etch capabilities, in preparation for futuristic devices su... » read more

Extending Copper Interconnects To 2nm


Transistor scaling is reaching a tipping point at 3nm, where nanosheet FETs will likely replace finFETs to meet performance, power, area, and cost (PPAC) goals. A significant architectural change is similarly being evaluated for copper interconnects at 2nm, a move that would reconfigure the way power is delivered to transistors. This approach relies on so-called buried power rails (BPRs) and... » read more

Blog Review: March 16


Ansys' Peter Hallschmid and Sandra Gely look at why, compared to rain and fog, snow is a different challenging environment for automotive sensors and how the random pattern of snowfall, properties of each flake, and the various distance between flakes play havoc on detecting objects. Siemens' Chuck Battikha focuses on how to protect against random hardware faults, the added costs of includin... » read more

Week In Review: Manufacturing, Test


Chipmakers Intel has announced a definitive agreement to acquire Tower, a specialty foundry vendor, for approximately $5.4 billion. With the acquisition of Tower, Intel expands its efforts in the foundry business, and put its rivals on notice. With Tower, Intel gains access to mature processes as well as specialty technologies, such as analog, CMOS image sensor, MEMS, power management and RF. ... » read more

Week In Review: Manufacturing, Test


Fabs Intel has announced plans for an initial investment of more than $20 billion in the construction of two new leading-edge fabs in Ohio. Planning for the first two factories will start immediately, with construction expected to begin late in 2022. Production is expected to come online in 2025. As part of the announcement, Air Products, Applied Materials, Lam Research and Ultra Clean Technol... » read more

200mm Shortages May Persist For Years


A surge in demand for chips at more mature process nodes is causing shortages for both 200mm foundry capacity and 200mm equipment, and it shows no signs of letting up. In fact, even with new capacity coming on line this year, shortages are likely to persist for years, driving up prices and forcing significant changes across the semiconductor supply chain. Shortages for both 200mm foundry cap... » read more

Blog Review: Jan. 19


Synopsys' Anand Thiruvengadam examines the memory chip design challenges of optimizing PPA, speeding turnaround time, and improving reliability and how a shift-left approach can help. Cadence's Paul McLellan checks out some of TSMC's recent updates in 3D packaging and the importance of thermal analysis and finding the right balance between IR-drop and TSV usage in multi-chip physical verific... » read more

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