Chip Industry Technical Paper Roundup: Feb. 18


New technical papers recently added to Semiconductor Engineering’s library: [table id=406 /] Find all technical papers here. » read more

FOWLP Warpage: Review Of Causes, Modeling And Methodologies For Controlling


A new technical paper titled "Warpage in wafer-level packaging: a review of causes, modelling, and mitigation strategies" was published by researchers at Arizona State University. Abstract "Wafer-level packaging (WLP) is a pivotal semiconductor packaging technology that enables heterogeneously integrated advanced semiconductor packages with high-density electrical interconnections through i... » read more

Universities Augment Engineering Curricula To Boost Employability


Increasing numbers of universities are offering semiconductor courses in their engineering programs, and also in math, physics, and business degrees. Most universities now offer a broad foundation so students can pivot to other industries during cyclical downturns, or when technology and science create entirely new and potentially lucrative opportunities, such as generative AI, advanced pack... » read more

Chip Industry Week In Review


The new Trump administration was quick to put a different stamp on the tech world: President Trump rescinded a long list of Biden’s executive orders, including those aimed at AI safety and the mandate for 50% EVs by 2030. Roughly 1.3 million EVs were sold in the U.S. in 2024, up 7.3% from 2023. The new administration announced $500 billion ($100 billion initially) in private sector in... » read more

Shortcutting Graduates’ Path To Productivity In Manufacturing And Test


Manufacturing, test, assembly, and analytics companies are finding unique ways to engage with universities in an effort to shore up the talent pipeline. The industry is recruiting graduates from universities across the U.S. while partnering with local institutes to serve specific needs. Industry/university co-operation includes: Mapping job descriptions Providing curricula frameworks... » read more

Chip Industry Week In Review


SK hynix started mass production of 1-terabit  321-high NAND, with availability scheduled for the first half of next year. Rapidus will receive an additional ¥200 billion yen ($1.28B) from the Japanese government beginning in fiscal year 2025, reports Nikkei. This is on top of ¥920 billion yen ($5.98B) Rapidus has already received from the government in support of its goal to reach commer... » read more

Chip Industry Technical Paper Roundup: Nov. 5


New technical papers recently added to Semiconductor Engineering’s library: [table id=378 /]   Further Reading Chip Industry Week In Review Silicon Valley design center and NY EUV Accelerator; Siemens’ big acquisition; Onto extends panel inspection with two acquisitions; DENSO-Quadric deal; thinner Si-based power wafer; $100M funding for AI; trade wars escalate; earnings rep... » read more

FPGA Fault Injection Attacks (ASU, KIT)


A new technical paper titled "Hacking the Fabric: Targeting Partial Reconfiguration for Fault Injection in FPGA Fabrics" was published by researchers at Arizona State University and Karlsruhe Institute of Technology (KIT). Abstract "FPGAs are now ubiquitous in cloud computing infrastructures and reconfigurable system-on-chip, particularly for AI acceleration. Major cloud service providers s... » read more

Americas Chip Funding Energizes Industry


This is the second in a series of articles tracking government chip investments. See part one here (global),  part 3 covering EMEA is here and Asia here. Since the first announcement of a non-binding preliminary memorandum of terms with BAE Systems in December 2023, the U.S. Department of Commerce has rolled out comprehensive plans to support more than a dozen companies in order to shore up... » read more

Research Bits: Sept. 24


Modeling negative capacitance Researchers from Lawrence Berkeley National Laboratory developed an open-source 3D simulation framework capable of modeling the atomistic origins of negative capacitance in ferroelectric thin films at the device level. When a material has negative capacitance, it can store a greater amount of electrical charge at lower voltages. The team believes the FerroX fra... » read more

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