HW-Accelerated Physical AI Framework For Resource-Constrained Edge Devices (ASU)


A new technical paper titled "Enabling Physical AI at the Edge: Hardware-Accelerated Recovery of System Dynamics" was published by researchers at Arizona State University. Abstract "Physical AI at the edge—enabling autonomous systems to understand and predict real-world dynamics in realtime—demands efficient hardware acceleration. Model recovery (MR), which extracts governing equations ... » read more

Annual Global IC Fabs And Facilities Report


Semiconductor companies announced a significant number of facilities in 2025 as global onshoring efforts continued across manufacturing, materials, packaging, design, and R&D. Investments came from both industry and government sources. Organizations worked together to solve current technology challenges, including soaring demand for AI chips and advanced memory, as well as complex applic... » read more

Chip Industry Technical Paper Roundup: Jan 6


New technical papers recently added to Semiconductor Engineering’s library: [table id=510 /] Find more semiconductor research papers here. » read more

Study Of HW Acceleration for Neural Networks (Arizona State Univ.)


A new technical paper titled "Hardware Acceleration for Neural Networks: A Comprehensive Survey" was published by researchers at Arizona State University. Abstract "Neural networks have become a dominant computational workload across cloud and edge platforms, but their rapid growth in model size and deployment diversity has exposed hardware bottlenecks that are increasingly dominated by mem... » read more

Chip Industry Technical Paper Roundup: Dec 22


New technical papers recently added to Semiconductor Engineering’s library: [table id=506 /] Find more semiconductor research papers here and in the most recent Chip Industry Week in Review. » read more

Structural Integrity Assessment of IC Packaging Using Scanning Acoustic Microscopy (Arizona State Univ., Fraunhofer IMWS)


A new technical paper titled "Recent Progress in Structural Integrity Evaluation of Microelectronic Packaging Using Scanning Acoustic Microscopy (SAM): A Review" was published by researchers at Arizona State University and Fraunhofer Institute for Microstructure of Materials and Systems IMWS. Abstract "Microelectronic packaging is crucial for protecting, powering, and interconnecting semi... » read more

Chip Industry Technical Paper Roundup: Dec. 2


New technical papers recently added to Semiconductor Engineering’s library: [table id=497 /] Find more semiconductor research papers here. » read more

Simplifying ESD Protection and Inter-Chiplet Signaling In Future 2.5D/3D Packaging Technologies (Arizona State, Univ. of Minnesota)


A new technical paper titled "Tiny Chiplets Enabled by Packaging Scaling: Opportunities in ESD Protection and Signal Integrity" was published by researchers at Arizona State University and University of Minnesota. Abstract: "The scaling of advanced packaging technologies provides abundant interconnection resources for 2.5D/3D heterogeneous integration (HI), thereby enabling the construction... » read more

LLMs Add Safety Risks To Physical AI


Humanoid robots with artificial general intelligence are some years from entering our daily life, but application-specific robotics are already here. From Amazon’s fleet of fulfillment center robots to robotic surgical systems in operating rooms, search and rescue robo-dogs, autonomous drones, and last-mile delivery robots, all the way down to the humble Roomba vacuum cleaner, physical AI sys... » read more

Chip Industry Week in Review


SEMICON West was held in Phoenix this week, with presentations covering heterogeneous integration, AI, quantum, supply chain resilience, and more. Amid the buzz of the conference, some key manufacturing and test announcements were made this week: The strategic importance of the Phoenix area hub was highlighted. Amkor Technology broke ground this week on its advanced packaging and test camp... » read more

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