Blog Review: Aug. 23


Siemens' Stephen Chavez discusses best practices when it comes to thermal analysis for PCB design, including component placement and close collaboration between mechanical and electrical engineering disciplines. Synopsys' Gary Ruggles, Richard Solomon, and Varun Agrawal introduce the Compute Express Link (CXL) specification and how it could help improve latency through computational offloadi... » read more

Blog Review: Aug. 16


Synopsys' Johannes Stahl and Tim Kogel suggest that multi-die systems require a new approach at the architecture planning phase and why chip designers can’t ignore physical effects such as layout, power, temperature, or IR-drop. Siemens' Rich Edelman argues for using the waveform window in a GUI rather than $display when debugging UVM. Cadence's Paul Scannell stresses the need for diver... » read more

Specialization Vs. Generalization In Processors


Academia has been looking at specialization for many years, but solutions were rejected because general-purpose solutions were advancing fast enough to keep up with most application requirements. That is no longer the case. The introduction and support of the RISC-V processor architecture has attracted a lot of attention, but whether that is the right direction for the majority of modern comput... » read more

Neon Intrinsics In Rust


At the end of 2021, the Neon intrinsics in Rust were completed and the community proposed stabilizing them (not requiring a nightly compiler). The implementation of the Neon intrinsics was a large effort mostly undertaken by the Rust community so Arm would like to thank everyone involved in that. At the time of writing, all the Neon intrinsics that are Armv8.0-A are implemented and are stabi... » read more

Arm Total Compute: Engineering For Tomorrow’s Workloads


As consumers seek richer and more immersive experiences from their devices, the way compute systems are engineered must continually evolve to keep up. Arm Total Compute takes a solution-focused approach to system-on-chip design, moving beyond individual IP elements to design and optimize the system as a whole to enable more digital immersion experiences. Not only does this white paper dis... » read more

Blog Review: Aug. 9


Synopsys' John Swanson and Manmeet Walia note that designing for 224G Ethernet will entail some unique considerations, as design margins will be extremely tight, making it mission-critical to optimize individual analog blocks to reduce impairments. Cadence's Rick Sanborn finds that knowing how best to debug common partitioning-related issues and implicitly control them using common features ... » read more

Chiplets: Deep Dive Into Designing, Manufacturing, And Testing


Chiplets are a disruptive technology. They change the way chips are designed, manufactured, tested, packaged, as well as the underlying business relationships and fundamentals. But they also open the door to vast new opportunities for existing chipmakers and startups to create highly customized components and systems for specific use cases and market segments. This LEGO-like approach sounds ... » read more

AI Transformer Models Enable Machine Vision Object Detection


The object detection required for machine vision applications such as autonomous driving, smart manufacturing, and surveillance applications depends on AI modeling. The goal now is to improve the models and simplify their development. Over the years, many AI models have been introduced, including YOLO, Faster R-CNN, Mask R-CNN, RetinaNet, and others, to detect images or video signals, interp... » read more

Blog Review: Aug. 2


Siemens' Katie Tormala points to the need for die attach thermal testing to ensure efficient removal of heat dissipation from power electronics components to prevent premature failure or thermal runaway. Synopsys's Dermott Lynch notes that over 30% of semiconductor failures are attributed to electrostatic discharge, with damage ranging from leakages and shorts to junction and metallization b... » read more

Battling Over Shrinking Physical Margin In Chips


Smaller process nodes, coupled with a continual quest to add more features into designs, are forcing chipmakers and systems companies to choose which design and manufacturing groups have access to a shrinking pool of technology margin. In the past margin largely was split between the foundries, which imposed highly restrictive design rules (RDRs) to compensate for uncertainties in new proces... » read more

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