PLANAR: A Programmable Accelerator For Near-Memory Data Rearrangement


Many applications employ irregular and sparse memory accesses that cannot take advantage of existing cache hierarchies in high performance processors. To solve this problem, Data Layout Transformation (DLT) techniques rearrange sparse data into a dense representation, improving locality and cache utilization. However, prior proposals in this space fail to provide a design that (i) scales with m... » read more

Blog Review: Oct. 12


Synopsys' Richard Solomon, Madhumita Sanyal, and Gary Ruggles take a look at the possibilities that CXL 3.0 can bring to a variety of data-driven applications that demand increasingly higher levels of memory capacity, with higher bandwidth, more security, and lower latency. Siemens EDA's Rich Edelman provides some tips for debugging UVM testbenches, such as how to determine what line changed... » read more

Week in Review: Design, Low Power


Could power beams be the key to smart city infrastructure and 5G/6G connectivity? A new report says both lasers and microwaves offer possible paths forward in this area, though both technologies come with benefits and drawbacks. Diminishing returns from process scaling, coupled with pervasive connectedness and an exponential increase in data, are driving broad changes in how chips are desi... » read more

Auto Safety Tech Adds New IC Design Challenges


The role of AI/ML in automobiles is widening as chipmakers incorporate more intelligence into chips used in vehicles, setting the stage for much safer vehicles, fewer accidents, but much more complex electronic systems. While full autonomy is still on the distant horizon, the short-term focus involves making sure drivers are aware of what's going on around them — pedestrians, objects, or o... » read more

The Automotive Paradigm Shift


We are currently experiencing a pivotal moment concerning the automotive industry. Three major technology areas are converging. First, there is an enormous demand for advanced driver-assistance systems (ADAS) coupled with the increasing trend toward autonomy. Second is the digitization and electrification of everything, which is driving the need for efficient compute. Third is the trend to high... » read more

Blog Review: Oct. 5


Arm's Andrew Pickard chats with Georgia Tech's Azad Naeemi and Da Eun Shim about an effort to evaluate the benefit of new interconnect materials and wire geometry and determine their impacts at the microprocessor level. Synopsys' Shekhar Kapoor shares highlights from a recent panel exploring the promises, challenges, and realities of 3D IC technology, including the potential of 3D nanosystem... » read more

IC Architectures Shift As OEMs Narrow Their Focus


Diminishing returns from process scaling, coupled with pervasive connectedness and an exponential increase in data, are driving broad changes in how chips are designed, what they're expected to do, and how quickly they're supposed to do it. In the past, tradeoffs between performance, power, and cost were defined mostly by large OEMs within the confines of an industry-wide scaling roadmap. Ch... » read more

Week In Review: Design, Low Power


Tools and IP Renesas introduced a new microprocessor that enables artificial intelligence to process image data from multiple cameras. "One of the challenges for embedded systems developers who want to implement machine learning is to keep up with the latest AI models that are constantly evolving,” said Shigeki Kato, Vice President of Renesas' Enterprise Infrastructure Business Division. �... » read more

Verification Methodologies Evolve, But Slowly


Semiconductor Engineering sat down to discuss digital twins and what is required to develop and verify new chips across a variety of industries, such as automotive and aerospace, with Larry Lapides, vice president of sales for Imperas Software; Mike Thompson, director of engineering for the verification task group at OpenHW; Paul Graykowski, technical marketing manager for Arteris IP; Shantanu ... » read more

Blog Review: Sept. 28


Cadence's Paul McLellan shares more highlights from the recent Hot Chips, including some very large chips and accelerators for AI and deep learning, new networks and switches, and mobile and edge processors. Synopsys' Marc Serughetti considers the different use cases for digital twins in automotive and how they can help determine the impact of software on verification, test, and validation a... » read more

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