Blog Review: Dec. 30


Cadence's Paul McLellan considers what the next ten years will look like for the RISC-V ISA with an expanding software ecosystem and increasing number of commercial and open cores available. Siemens EDA's Harry Foster checks out the languages and libraries being used to design and verify FPGAs and how they've changed over the last several years. Synopsys' Jonathan Knudsen contends that IT... » read more

2020: A Turning Point In The Chip Industry


At the start of 2020, most of the industry was upbeat and sales forecasts for the year were good. Then the pandemic hit, and fear gripped most of the industry — but not for long. New markets emerged, demand increased, and the levels of innovation went far beyond what had been forecast. While hope is on the horizon that the virus will be contained during 2021, life will not return to the ol... » read more

Blog Review: Dec. 23


Cadence's Paul McLellan checks out how Arm is becoming a powerhouse in the server and high-end space with the addition of new R&D and a focus on getting the most out of its architecture. Siemens EDA's Harry Foster continues his look at verification trends in FPGAs by checking out adoption of different simulation and formal technologies. Synopsys' Taylor Armerding looks ahead to 2021 w... » read more

RISC-V Verification Challenges Spread


The RISC-V ecosystem is struggling to keep pace with rapid innovation and customization, which is increasing the amount of verification work required for each design and spreading that work out across more engineers at more companies. The historical assumption is that verification represents 60% to 80% or more of SoC project effort in terms of cost and time for a mature, mainstream processor... » read more

Industry Transformations In 2021 And Beyond


Last December, the name of my predictions blog summarized my view crisply, which is that "applications, ecosystems and system complexity will be key verification drivers for 2020." Slam dunk on these. Application domains significantly impacted verification aspects in 2020. Who would have thought that Facebook and AWS would be among the keynotes at our user conference, speaking about how thei... » read more

Week In Review: Design, Low Power


Tools, Cloud, IP Valtrix Systems updated its STING design verification tool for RISC-V based CPU and SoC implementations. Version 1.9.0 adds support to verify recent changes to the RISC-V user and privilege specifications, including draft versions of the vector and bit manipulation standard extensions. Preliminary support for the draft version of the RISC-V hypervisor extension has also been a... » read more

Week In Review: Auto, Security, Pervasive Computing


Automotive Austin, Texas-based automotive startup Uhnder raised $45 million in Series C funding for its digital radar-on-chip. Telechips, a fabless semiconductor company that works on automotive SoCs, is using Arm’s IP to design its Dolphin5 SoC for ADAS (advanced drive assistance systems) and digital cockpits with in-vehicle infotainment (IVI). Dolphin5 will include the Arm’s Mali-G78A... » read more

Blog Review: Dec. 16


Arm's Benoit Labbe investigates why battery monitoring is so important for a low-power microcontroller and shows how it was implemented in the M0N0 MCU while drawing a fraction of a nW in typical conditions. Siemens EDA's Harry Foster takes a look at how much of their time FPGA design engineers spend on verification, and the tasks that keep verification engineers the busiest. Synopsys' Sc... » read more

Low Power Still Leads, But Energy Emerges As Future Focus


In 2021 and beyond, chips used in smartphones, digital appliances, and nearly all major applications will need to go on a diet. As the amount of data being generated continues to swell, more processors are being added everywhere to sift through that data to determine what's useful, what isn't, and how to distribute it. All of that uses power, and not all of it is being done as efficiently as... » read more

Standard Benchmarks For AI Innovation


There is no standard measurement for machine learning performance today, meaning there is no single answer for how companies build a processor for ML across all use cases while balancing compute and memory constraints. For the longest time, every group would pick a definition and test to suit their own needs. This lack of common understanding of performance hinders customers' buying decis... » read more

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