Blog Review: June 24


Cadence's Paul McLellan provides an overview of the new IEEE 1838 standard for manufacturing test of 3D stacked ICs and how it aims to enable testing of multi-die chiplet-based designs. In a video, Mentor's Colin Walls investigates the scope and lifetime of pointers in embedded applications. A Synopsys writer checks out the latest mobile memory standard, JESD209-5A, and the enhancements i... » read more

Challenges In Building Smarter Systems


Semiconductor Engineering sat down to define what the edge will look like with Jeff DeAngelis, managing director of the Industrial and Healthcare Business Unit at Maxim Integrated; Norman Chang, chief technologist at Ansys; Andrew Grant, senior director of artificial intelligence at Imagination Technologies; Thomas Ensergueix, senior director of the automotive and IoT line of business at Arm; V... » read more

Week In Review: Manufacturing, Test


Chipmakers and OEMs At next week’s Apple Worldwide Developers Conference, Apple is expected to roll out its long-awaited Arm-based Mac computers. This could provide a boost for Apple’s foundry vendor as well as equipment makers. It’s the worst-kept secret in the industry. As reported by the Apple sites, Apple is moving from Intel’s microprocessors to its own Arm-based chips for th... » read more

Week In Review: Design, Low Power


Tools & IP Rambus debuted 112G XSR/USR PHY IP on TSMC's N7 7nm process. The PHY IP enables die-to-die and die-to-optical engine connectivity for chiplets and co-packaged optics targeting data center, networking, 5G, HPC, and AI/ML applications. It has been demonstrated in silicon to exceed the reach/BER performance of the CEI-112G XSR specification and supports NRZ and PAM-4 signaling at v... » read more

Week In Review: Auto, Security, Pervasive Computing


Security Many IoT devices have some of the 19 bugs known as Ripple20 vulnerabilities. Researchers JSOF discovered the security flaws in library produces by Treck, Inc., which is used in many IoT devices. Edge, cloud, data center Rambus delivered its 112G XSR/USR PHY IP on TSMC 7nm process (N7). The SerDes PHY was designed for chiplets and co-packaged optics (CPO) architectures that are des... » read more

Different Levels Of Interconnects


The interconnect hierarchy from metal 0 in a semiconductor all the way up to racks of servers. Kurt Shuler, vice president of marketing at Arteris IP, explains why each one is different, and how every level can contribute to latency and performance. » read more

Blog Review: June 17


Mentor's Chris Spear provides an introduction to SystemVerilog Multidimensional Arrays and shares code samples to follow along. Cadence's Paul McLellan listens in on Sophie Wilson's 2020 Wheeler Lecture that traces the history of the microprocessor from the early days of Moore's Law through to increasing power and economic constraints that are causing a transition from general purpose to spe... » read more

Simplifying And Speeding Up Verification


Semiconductor Engineering sat down to discuss what's ahead for verification with Daniel Schostak, Arm fellow and verification architect; Ty Garibay, vice president of hardware engineering at Mythic; Balachandran Rajendran, CTO at Dell EMC; Saad Godil, director of applied deep learning research at Nvidia; Nasr Ullah, senior director of performance architecture at SiFive. What follows are excerpt... » read more

Interconnect Challenges Grow, Tools Lag


Interconnects are becoming much more problematic as devices shrink and the amount of data being moved around a system continues to rise. This limitation has shown up several times in the past, and it's happening again today. But when the interconnect becomes an issue, it cannot be solved in the same way issues are solved for other aspects of a chip. Typically it results in disruption in how ... » read more

AI, 5G, IoT Combine In The Fifth Wave Of Computing


Something hugely positive is happening as a result of AI, 5G and the Internet of Things (IoT) reaching maturity at the same time. Like three kids growing up together, these technologies are feeding off each other’s energy and enhancing each other’s impact on the world. It’s this union, far greater than the sum of its parts, that I call the Fifth Wave of Computing. Why the fifth? We�... » read more

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