Week In Review: Auto, Security, Pervasive Computing


Security The U.S. Defense Advanced Research Projects Agency (DARPA) selected Synopsys as the main contractor to provide SoC design tools and security IP for its Automatic Implementation of Secure Silicon (AISS) program. The four-year program’s goal to develop a design tool and IP ecosystem to automate adding security into integrated circuits. Synopsys will be working on a research team with ... » read more

The Fast, ‘Attractive’ Path From Great PPA To The Best PPA For High-Performance Arm Cores


By Mark Richards and Neel Desai When you want to create a website for your new side-hustle, or maybe for your local soccer team, it's rare that you would order a book on cascading-style sheets, break out the HTML editor and start from a blank sheet of “paper.” You'd do the smart thing and use a website builder, link it to some content management tool (this would get you to 90% of a usabl... » read more

Open-Source Hardware Momentum Builds


Open-source hardware continues to gain ground, spearheaded by RISC-V — despite the fact that this processor technology is neither free nor simple to use. Nevertheless, the open-source hardware movement has established a solid foothold after multiple prior forays that yielded only limited success, even for processors. With demand for more customized hardware, and a growing field of startups... » read more

2020 CEO Outlook


Semiconductor Engineering sat down to discuss the semiconductor industry's outlook and what's changing with Simon Segars, CEO of Arm; Joseph Sawicki, executive vice president of IC EDA at Mentor, a Siemens Business; Raik Brinkmann, CEO of OneSpin Solutions; Babak Taheri, CEO of Silvaco; John Kibarian, CEO of PDF Solutions; and Prakash Narain, CEO of Real Intent. The conversation was part of the... » read more

Blog Review: June 24


Cadence's Paul McLellan provides an overview of the new IEEE 1838 standard for manufacturing test of 3D stacked ICs and how it aims to enable testing of multi-die chiplet-based designs. In a video, Mentor's Colin Walls investigates the scope and lifetime of pointers in embedded applications. A Synopsys writer checks out the latest mobile memory standard, JESD209-5A, and the enhancements i... » read more

Challenges In Building Smarter Systems


Semiconductor Engineering sat down to define what the edge will look like with Jeff DeAngelis, managing director of the Industrial and Healthcare Business Unit at Maxim Integrated; Norman Chang, chief technologist at Ansys; Andrew Grant, senior director of artificial intelligence at Imagination Technologies; Thomas Ensergueix, senior director of the automotive and IoT line of business at Arm; V... » read more

Week In Review: Manufacturing, Test


Chipmakers and OEMs At next week’s Apple Worldwide Developers Conference, Apple is expected to roll out its long-awaited Arm-based Mac computers. This could provide a boost for Apple’s foundry vendor as well as equipment makers. It’s the worst-kept secret in the industry. As reported by the Apple sites, Apple is moving from Intel’s microprocessors to its own Arm-based chips for th... » read more

Week In Review: Design, Low Power


Tools & IP Rambus debuted 112G XSR/USR PHY IP on TSMC's N7 7nm process. The PHY IP enables die-to-die and die-to-optical engine connectivity for chiplets and co-packaged optics targeting data center, networking, 5G, HPC, and AI/ML applications. It has been demonstrated in silicon to exceed the reach/BER performance of the CEI-112G XSR specification and supports NRZ and PAM-4 signaling at v... » read more

Week In Review: Auto, Security, Pervasive Computing


Security Many IoT devices have some of the 19 bugs known as Ripple20 vulnerabilities. Researchers JSOF discovered the security flaws in library produces by Treck, Inc., which is used in many IoT devices. Edge, cloud, data center Rambus delivered its 112G XSR/USR PHY IP on TSMC 7nm process (N7). The SerDes PHY was designed for chiplets and co-packaged optics (CPO) architectures that are des... » read more

Different Levels Of Interconnects


The interconnect hierarchy from metal 0 in a semiconductor all the way up to racks of servers. Kurt Shuler, vice president of marketing at Arteris IP, explains why each one is different, and how every level can contribute to latency and performance. » read more

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