2020 CEO Outlook

Impacts of the global pandemic and the rising cost of chip design.


Semiconductor Engineering sat down to discuss the semiconductor industry’s outlook and what’s changing with Simon Segars, CEO of Arm; Joseph Sawicki, executive vice president of IC EDA at Mentor, a Siemens Business; Raik Brinkmann, CEO of OneSpin Solutions; Babak Taheri, CEO of Silvaco; John Kibarian, CEO of PDF Solutions; and Prakash Narain, CEO of Real Intent. The conversation was part of the ESD Alliance’s annual outlook, which this year was held virtually. (Part 2 is here. and part 3 is here )

SE: Everybody has been dealing with the fallout of the coronavirus pandemic. What impact do you see this having on jobs and on consumer spending, and how will that affect the semiconductor industry going forward? There is no shortage of opinions out there, and they seem to vary almost by the day.

Segars: If you look at the range of forecasts for the economy, for the tech industry, for shipments of various end products, it really is all over the place. And it does, as you say, change every day. We look very carefully at different segments of the industry for costs and for shipments, and what that implies for the supply chain. When you add 16 million unemployed people in a month, it’s going to have some impact on consumer spending. You just have to assume that. But what we’re seeing from talking to our partners across the industry is that, despite all of that going on, and despite recognition that in the near term volumes are likely to be depressed, there’s a ton of design activity going on, as well. That’s what’s really encouraging. Despite COVID-19, the long-term trends aren’t being affected. We see lots and lots of people really leaning into what do they need to have technology-wise to succeed when we come out of this crisis, and doing the work now to set themselves up for success.

Taheri: In the short term we have to ensure the supply chain and maintain cyber vigilance. We’ve seen many instances of where people were not careful or were not protected. To be able to do that, we have to keep our employees healthy. There are so many guidelines and rules that in mid-March, I wrote a 32-page article on LinkedIn about what are the best practices in terms of keeping employees healthy in the short term. Mid-term, there will be investment impacts on 5G, AI, IoT, and autonomous things. And long-term, we will have to revise business continuity plans. We have to implement a lot of technology upgrades and collaborations in terms of cloud and automation technology, which will come at a cost.

Brinkmann: We see some acceleration of digitalization across industries. Some of the industries that are not digitalized are suffering the most right now. If you look at things like automotive/transportation production, in the long term there will be a need for innovation and investment in chip designs. If the trucks that were stuck inside the borders of Germany and Poland, or wherever supply chains were disrupted, were all autonomously driven, this pandemic would have had a less negative effect. So maybe this will spark some innovation in this area that will, in the near term and long term, lead to more investment in chip design. On the short-term front, of course, you see beneficiaries like cloud services, virtual presence meetings, gaming, which already have increased demand for new chips. This is a short-term positive effect. In the long run, we can hope that positive effects dominate. But for now, we don’t see any slowdown in design activity, either.

Sawicki: When you look at the aspects of what will happen to the overall economy in general markets, it’s really hard to call some of these things forecasts at this point. There are a lot of guesstimates. It’s hard to track what happens when you instantly take 25% of a population and send them home, either furloughed or unemployed. But there are aspects that I find really fascinating about how this affects tech. We have areas that make us somewhat resilient to this. There’s design activity and manufacturing activity. Design activity transitioned to ‘work from home’ in a way where I was actually surprised at how naturally it occurred, and how productive people have been. We had started monitoring this a number of years ago, and the bottom line did not move. With manufacturing, many of the hotspots that we’ve had in Oregon have been due to particular manufacturing plants that is causing people to not have enough distance. A fab is a pretty nice place to be during pandemic in terms of how well protected you are. And if you look at the overall trends that are going to come out of this, I don’t know what work looks like in a year, but it’s hard to imagine that you don’t end up having a greater reliance upon technology-enabled communications, interactions, digitalization, which are all driving very positive trends for the semiconductor industry itself. So we’ve got an overall outlook that is almost unknowable, some good trends within the semiconductor space, and some very positive resilience as demonstrated by at least the design chain to date.

Kibarian: We went into this pandemic assuming it was going to be super negative to the business. We’ve been surprised by how many of the customers actually have said their business is doing quite well. Even our customers in the automotive space have been more resilient than we expected. If you just look at the the amount of stimulus that the [U.S.] government has put in to the hands of people, the savings rate went up in April and May meaningfully. It was about a 10% increase in the amount of savings for the average American because they couldn’t spend money. And even for those making minimum wage that were unemployed, the stimulus checks for some were greater than what they were making as workers. The challenge, and the reason that everyone’s forecast is just a guesstimate, is that nobody really understands what will happen when that stops. Will a new economy emerge or not? And what does it look like? We all recognize it’s not the same economy we had before. We can’t travel like we traveled before — at least not for the next year or so. And we will spend money in other ways, and tech will be a net beneficiary. But whether we are impacted negatively is unclear. Will the stimulus be able to carry the economy through a massive transition? And as Joe said, we were able to shift to working from home as an industry almost overnight, and we have been surprisingly productive. If the stimulus carries companies through that transition and people are able to spend, there will be winners and losers, but overall the economy may not be as bad as it felt like it was going to be in April.

Narain: We talk about work and productivity, but there’s also a major lifestyle change. With isolation, it’s not just about working from home. It’s also entertainment from home, and doing everything from home. So we are looking at a problem, but we also are looking at opportunities because there will be a change in lifestyle in the work environment. We are in the infrastructure segment. Our customers are building infrastructure to be able to take advantage of these opportunities. We don’t see any slowdown. In fact, if anything, we see increasing opportunity in front of us in the verification space, primarily because we don’t see any slowdown in the design activity.

SE: Another big challenge the industry has been facing recently – and we’ve been watching this coming since the introduction of finFETs — is that it’s getting more and more expensive to design and manufacture chips. In the past, if you moved to the next node, at least the price per transistor would go down. That’s no longer the case. We’re now thinking about dollars per unit of performance per watt, and even that’s increasing. What impact will this have?

Taheri: As technology nodes shrink, a lot of Moore’s Law assumptions are not there. Even when we talk about 7nm finFET technology, it’s not really the gate length. If you take into account the cost, the labor, the material, and everything that goes into it, going from 28nm to 20nm there’s a 22% cost increase, and moving to 7nm it’s about 14% higher cost than 10nm. There are a handful of companies that need to get to those technology nodes, and they can afford it. But the mask costs for the layers of metal have increased because as you squeeze transistors, you have to stack up a lot more metals. The bottom line, though, is time is always on your side with every technology node that’s new, and we’ve known this historically for the past four decades. It’s expensive when it comes out, but as time goes by it gets cheaper. So for the companies that cannot afford it, they can get on multi-project wafers, or wait awhile, or look at alternative technology nodes for low power, low cost and good density. You also may want to go look at adjacent technologies from CMOS, such as FD-SOI, with a high resistivity substrate, and so on.

Narain: I am looking at things from a totally different perspective, which is the front end. If you look at the factors driving design, time-to-market plays a very important role. And traditionally, the level of optimization required in designs could have been lower. You could jump to a different process node and have more gates and still be able to get your functionality and design out in time. But now, if that slows down, what we’ve seen our customers say is they have to innovate more on their design methodologies. This is causing adjustments in the design flows. They are becoming more efficient, more oriented toward a shift left, and they are doing better design planning on the front end. We are seeing a lot of need for new solutions that will enable this greater efficiency.

Brinkmann: The front-end design perspective is coming more from an architectural point of view. Specifically in IoT and edge, when you have applications that are not as accessible and you have a longer lifetime for systems like automotive, you cannot afford to bring out new things all the time. That actually plays well with the idea of heterogeneous customizable platforms that we see coming. So Xilinx devices have processors, accelerators, FPGA and I/O. We see that in other places, as well. The availability of chiplets and advanced packaging make this even more interesting. So you basically have customized instruction set architectures targeted toward a specific market. Arm has opened up the ISA, and you see RISC-V being customized. We have custom accelerators for certain machine learning tasks attached to that, and configurability in hardware and software. If you look at the second generation of the Infineon automotive microcontroller, it has more than a million user-controlled registers, and that’s because the lifetime of these systems is so long that you have to address different markets, different applications over time. Also, the engineering cost for the development and the application is very expensive. And last but not least, customizability is also seen in field programmable logic, where you have an eFPGA or FPGA either in the same package, in the same chip, or on the side on the on the system. Now, the consequence of that is it leads to a huge number of combinations that you need to verify, and traditional techniques don’t really help. On top of that, these platforms live so long that you have a continuous design environment. People update their systems for security reasons, for functionality updates, and for other things, and an interesting aspect is that the design verification activity then extends over the lifetime. So you no longer just ship the chip and forget about it. You need to implement things like DevOps or PLM techniques to design and verify over the lifetime of the system, even after chip is already in use. This is being driven by different vectors and the cost of silicon.

Segars: The cost is only going up. Feature sizes have been reduced by an order of magnitude, and design costs have gone up by an order of magnitude. Because people are able to build much more complex sophisticated chips with billions of transistors, they can throw them in. But that raises challenges around verification, and just proving that your functionality is correct. So those costs have been going through the roof. And then there is all the software that you run on top of it, which gets ever more complex. These trends have been going on for a long time and they have been driving a lot of the consolidation that we’ve seen in the semiconductor space. That will continue because some of the fundamental costs — the cost of all the tooling, the cost of developing verification methodologies, the cost of porting IP from one node to the next — you’ve got to be able to amortize that across a number of designs. You’ve got to have large companies at scale to be able to do that. While M&A has been on a bit of a hiatus through the COVID-19 crisis, I’m pretty sure we’ll see another surge of that coming out, which leads to big companies getting bigger. Now, on the other hand, there’s a whole bunch of other techniques which are feasible — putting multiple dies down on a chip, integrating FPGA as was just mentioned — all of those things will help. But fundamentally, complexity is going up, and as an industry we’ve got to work on helping contain that complexity or it will come back to haunt us later on. Things like AI can help contain the verification challenge. But I do think the net of all of this complexity means that it will drive more consolidation in our industry.

Sawicki: Emphatically, you can see the trends in terms of design costs having increased. There’s this premise that Moore’s Law is dead, as well. That must have started 10 to 15 years ago. And I have this one chart that’s been in virtually every presentation I’ve given for six years now. Every time Apple comes out with an application processor, you get more details in terms of area transistors in performance than you get anyplace else. And I’ve just charted what happens with Apple’s chips every year. For the last 10 years, the performance, power, density — all of this has been increasing directly on a Moore’s Law pace. And I believe cost per transistor continues to go down. Now we have been hit by one really nasty effect, which is Dennard scaling is dead. So all the power gains don’t come just by shrinking devices. They have to come from materials science, with new types of transistors and new architectural approaches. And all of those prove you can still achieve these things. They just become harder. What drives a lot of integration of things like chiplets is that, because we’re building these far more complex systems and they require more analog and memory, there’s a real systems benefit by being able to put those things into package rather than on board. That’s going to be one of the more amazing trends going forward. As those devices become multi-chip packages that can give you a system performance, that will cause an ability to capture far more functionality. That’s where things get really interesting.

Note: this is part 1 of a multi-part series.

Related Articles
Chip Reliability Vs. Cost (part 2 of above roundtable)
CEO Outlook: Market shifts, higher productivity per engineer and the overhead and opportunities for security and reliability.
Challenges For A Post-Moore’s Law World
More customization and a different message for the chip industry.

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