tag: Arteris IP

Lab-To-Fab Testing
By Ed Sperling - 08 Oct, 2018 - Comments: 0

Test equipment vendors are working on integrating testing and simulation in the lab with testing done later in the fab, setting the stage for what potentially could be the most significant change in semiconductor test in years. If they are successful, this could greatly simplify design for test, which has become increasingly difficult as chips get more complex, denser, and as more heterogene... » read more

Week in Review: IoT, Security, Auto
By Jeff Dorsch - 05 Oct, 2018 - Comments: 0

Internet of Things Amazon Web Services announced that Iridium Communications has joined the AWS Partner Network. AWS and Iridium have collaborated on development of Iridium CloudConnect, a service that enables worldwide coverage for Internet of Things applications through Iridium’s satellite network. AWS IoT is being paired with Iridium IoT services as a result. IHS Markit forecasts there wi... » read more

Week In Review: Design, Low Power
By Jesse Allen - 05 Oct, 2018 - Comments: 0

Mirabilis Design debuted an AI-driven tool for performance analysis and architecture exploration of SoCs and embedded systems. VisualSim AI Processor Generator creates pipeline-accurate models that have port integration with standard buses and memories, which is used to compare different processor families, optimize the specification and identify system bottlenecks. The generated model supports... » read more

A Primer On Last-Level Cache Memory For SoC Designs
By Kurt Shuler - 06 Sep, 2018 - Comments: 0

System-on-chip (SoC) architects have a new memory technology, last level cache (LLC), to help overcome the design obstacles of bandwidth, latency and power consumption in megachips for advanced driver assistance systems (ADAS), machine learning, and data-center applications. LLC is a standalone memory that inserts cache between functional blocks and external memory to ease conflicting requireme... » read more

Artificial Intelligence Chips: Past, Present and Future
By Ty Garibay - 02 Aug, 2018 - Comments: 0

Artificial Intelligence (AI) is much in the news these days. AI is making medical diagnoses, synthesizing new chemicals, identifying the faces of criminals in a huge crowd, driving cars, and even creating new works of art. Sometimes it seems as if there is nothing that AI cannot do and that we will all soon be out of our jobs, watching the AIs do everything for us. To understand the origins ... » read more

Week In Review: Design, Low Power
By Jesse Allen - 13 Jul, 2018 - Comments: 0

M&A Intel will acquire fabless company eASIC. Founded in 1999, eASIC sells structured ASIC platforms that act as a midpoint between FPGAs and standard cell ASICs by combining FPGA-like logic and design flows with single via routing. Eventually, Intel sees potential in using its Embedded Multi-Die Interconnect Bridge (EMIB) technology to combine Intel FPGAs with structured ASICs in a system... » read more

Week In Review: Design, Low Power
By Jesse Allen - 29 Jun, 2018 - Comments: 0

M&A Siemens acquired Austemper Design Systems, which provides tools for functional safety and safety-critical designs. Founded in 2015, Texas-based Austemper adds state-of-the-art safety analysis, auto-correction and fault simulation technology to address random hardware faults, as well as correct and harden vulnerable areas, subsequently performing fault simulation to ensure the design is... » read more

Tuesday At DAC 2018
By Brian Bailey - 27 Jun, 2018 - Comments: 0

The morning starts with the Accellera Breakfast. Accellera has made some significant progress this year and we can expect to hear about the approval of the Portable Stimulus 1.0 specification later in the conference as well as the initial release of SystemC CCI as well as a proposal for the creation of an IP Security Assurance Working Group, which will discuss standards development to address s... » read more

The Week In Review: Design
By Jesse Allen - 08 Jun, 2018 - Comments: 0

Tools & IP Synopsys added machine learning capabilities to its Design Platform. The company highlighted benefits to the PrimeTime signoff tool, which saw 5X faster power recovery in customer designs at leading-edge geometries. Renesas is using the tool, noting a 4X power ECO speed-up. ArterisIP unveiled a standalone last level cache (LLC) for high-performance SoCs. CodaCache can be adde... » read more

Power Optimization Strategies Widen
By Brian Bailey - 10 May, 2018 - Comments: 0

An increasing amount of electronic content in new and existing markets is creating different and sometimes competing demands for power optimization. For the past decade, EDA has been driven by the mobile phone industry, where the emphasis is on better power analysis and optimization tools to reduce power consumption and extend battery life. While energy efficiency continues to improve, other... » read more

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