2.5D, ASICs Extend to 7nm

By Mark LaPedus - 13 Jun, 2017 - Comments: 2

The leading-edge foundry market is heating up. For example, GlobalFoundries, Intel, Samsung and TSMC have recently announced their new and respective processes. The new processes from vendors range anywhere from 10nm to 4nm, although the current battle is taking place at 10nm and/or 7nm. In fact, one vendor, GlobalFoundries, this week will describe more details about its previously-announced... » read more

Moore’s Law: A Status Report

By Ed Sperling - 20 Apr, 2017 - Comments: 3

Moore's Law has been synonymous with "smaller, faster, cheaper" for the past 52 years, but increasingly it is viewed as just one of a number of options—some competing, some complementary—as the chip industry begins zeroing in on specific market needs. This does not make [getkc id="74" comment="Moore's Law"] any less relevant. The number of companies racing from 16/14nm to 7nm is higher t... » read more

Biz Talk: ASICs

By Ed Sperling - 27 Mar, 2017 - Comments: 0

eSilicon CEO [getperson id="11145" comment="Jack Harding"] talks about the future of scaling, advanced packaging, the next big things—automotive, deep learning and virtual reality—and the need for security. [youtube vid=leO8gABABqk] Related Stories Executive Insight: Jack Harding (Aug 2016) eSilicon’s CEO looks at industry consolidation, competition, China’s impact, an... » read more

Intel To Buy Mobileye

By Ed Sperling - 13 Mar, 2017 - Comments: 2

Intel today said it would acquire embedded vision leader Mobileye for roughly $15.3 billion in equity—$14.7 billion in "enterprise value"—setting the stage for a huge push by the chipmaker into the autonomous driving market. Intel has been dabbling in the automotive market for some time, starting with an unsuccessful bid to replace 8-bit microcontrollers with low-end processors. With the... » read more

Better Code With RTL Linting And CDC Verification

By Sergei Zaychenko - 23 Feb, 2017 - Comments: 0

Automated design rule checking, or linting, has been around in RTL verification for at least a couple decades, yet still many HDL designers completely ignore this simple yet very powerful bug hunting method. Why would a busy designer need to run this annoying warning generator? The hostility against using conventional linting tools is often explained by the enormous amount of output noise, limi... » read more

Too Big To Simulate?

By Ann Mutschler - 27 Oct, 2016 - Comments: 2

With system design complexity set on a steady upward trajectory, there are situations in which traditional simulation just can’t keep up. The alternative—and one being used by Google, Uber, Ford, GM, Volvo, Audi and others with autonomous vehicles— is to test cars on the road and collect data for later analysis. “They're not simulating, they're just doing it all in the real world ... » read more

On The Verge

By Mike Gianfagna - 27 Apr, 2016 - Comments: 0

Anyone who has been following the IoT/IoE or whatever-you-want-to-call-it movement knows we’re on the eve of far-reaching, life-altering change. There will be billions of connected devices, all streaming information to gigascale cloud datacenters using big data analytics and deep machine learning. Somewhere along the way, we’ll discover important, useful information from all this tha... » read more

Charting A New Course For Semiconductors

By Rambus - 09 Mar, 2016 - Comments: 0

The semiconductor industry is at an inflection point facing challenges, including rising development costs, shrinking margins, market saturation and unprecedented consolidation. Although no stranger to boom and bust cycles, semiconductor companies are actively seeking a return to stability via a more sustainable and collaborative business paradigm. In this context, Rambus and the Global S... » read more

FPGA’s Role Expands

By Ann Mutschler - 10 Sep, 2015 - Comments: 1

For more than a decade FPGA vendors argued that FPGAs would become a viable alternative to ASICs, adding programmability along with the same kind of advances in performance and power that ASICs saw at each new process node. While that never played out as they expected, FPGAs nonetheless have carved out a formidable position in the semiconductor market. Generally speaking, FPGAs today are us... » read more

High Throughput GSPS Signal Processing For FPGAs And ASICs Using Synthesizable IP Cores

By Synopsys - 24 Sep, 2014 - Comments: 0

This whitepaper illustrates how parallel processing synthesizable [getkc id="43" comment="IP"] cores available in Synphony Model Compiler enable Giga Samples Per Second (GSPS) throughput on FPGAs, and efficient area/power trade-offs for ASIC targets. In particular, we demonstrate how Parallel FFT, FIR, and CIC blocks enable users to scale throughput beyond achievable clock frequencies, and/or r... » read more

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Knowledge Centers
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The critical, and growing, significance of mature node chips and processes.

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Focus is on letting engineers do much more with the same or fewer resources — and less drudgery.

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eBook: Nearly everything you need to know about memory, including detailed explanations of the different types of memory; how and where these are used today; what's changing, which memories are successful and which ones might be in the future; and the limitations of each memory type.

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tag: ASICs

2.5D, ASICs Extend to 7nm

Moore’s Law: A Status Report

Biz Talk: ASICs

Intel To Buy Mobileye

Better Code With RTL Linting And CDC Verification

Too Big To Simulate?

On The Verge

Charting A New Course For Semiconductors

FPGA’s Role Expands

High Throughput GSPS Signal Processing For FPGAs And ASICs Using Synthesizable IP Cores

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Knowledge Centers
Entities, people and technologies explored