Testing the Waters


By Ann Steffora Mutschler Large semiconductor companies are now testing the waters in 3D design to determine how to best leverage the technology for lower power, better performance and additional architectural flexibility. As such, much work is being done to determine how exactly to achieve an optimum 3D design outcome. 3D is almost by definition an architectural approach to power sav... » read more

Experts At The Table: Pain Points


By Ed Sperling Low-Power/High-Performance Engineering sat down with Vinod Kariat, a Cadence fellow; Premal Buch, vice president of software engineering at Altera; Vic Kulkarni, general manager of Apache Design; Bernard Murphy, CTO at Atrenta, and Laurent Moll, CTO at Arteris. What follows are excerpts of that conversation. LPHP: Where will the pain points be going forward? Kariat: 20nm is... » read more

Experts At The Table: Does 20nm Break System-Level Design?


By Ann Steffora Mutschler System-Level Design sat down to discuss design at 20nm with Drew Wingard, chief technology officer at Sonics; Kelvin Low, deputy director of product marketing at GlobalFoundries, Frank Schirrmeister, group director of product marketing for system development in the system and software realization group at Cadence; and Mike Gianfagna, vice president of marketing at Atr... » read more

Experts At The Table: IP Subsystems


By Ed Sperling Semiconductor Manufacturing & Design sat down to discuss the transition to IP subsystems with Kevin Meyer, vice president of design enablement strategy and alliances at GlobalFoundries; Steve Roddy, vice president of marketing at Tensilica; Mike Gianfagna, vice president of marketing at Atrenta; and Adam Kablanian, CEO of Memoir Systems. What follows are excerpts of that con... » read more

Atrenta Buys NextOp


By Ed Sperling Atrenta said today it will acquire NextOp Software, a formal tools startup that was created in 2006 and which came out of stealth mode in 2010. The move is interesting as much from a business perspective—it pits Atrenta against Jasper Design Automation, at least in the narrow assertion synthesis and assertion generation markets—as what it says about the increasing interes... » read more

Reducing Circuitry To Reduce Power


By Ann Steffora Mutschler Power is at the top of the list of concerns for design teams today. Consequently, engineers are constantly looking at new techniques and architectural approaches to lower and management the power and energy consumption of their devices. This has resulted in some incredible engineering feats, turning parts of a device on and off as needed, applying different volta... » read more

Getting Formal With Power


By Ed Sperling Formal methodologies have always been an important tool in the verification engineer’s toolbox because they often can pinpoint bugs faster and with more accuracy than other verification approaches. The problem is that most engineers don’t know how to use them, and understanding this technology to a proficiency level requires a learning curve that most engineers consider pain... » read more

Lint Your Hardware Description: The Need To Be Fast, Accurate, Scalable And Flexible


A reliable linting tool must be SAFE (Scalable, Accurate, Fast and Extendible) so it can help catch issues early in the design cycle - issues that may be missed by traditional dynamic verification techniques. The main objective of a SAFE linting solution is to reduce costly design iterations, prevent late stage design ECOs and promote seamless reuse of IPs. Such a linting solution will need to ... » read more

Low Power Everywhere


By Kiran Vittal School is over for my kids and the summer holidays are here. We are planning to make minor modifications to our home, which includes installation of recessed lights. LED light bulbs are all over the place in home appliance stores and they claim 85% savings in energy costs with a life span of 50,000 hours. The cost of these LED bulbs is five to six times the cost of your average... » read more

Experts At The Table: Black Belt Power Management


By Ann Steffora Mutschler With approximately 80% of SoC content reused from past designs or brought in from internal and external IP sources, a significant part of a design engineer’s job today is writing glue logic and verifying to make sure the integrated system communicates as dictated by the specification. Integration challenges continue to mount with the increasing amount of black ... » read more

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