tag: AXI

An Easier Path To Faster C With FPGAs
By Zibi Zalewski - 22 Nov, 2016 - Comments: 0

For most scientists, what is inside a high-performance computing platform is a mystery. All they usually want to know is that a platform will run an advanced algorithm thrown at it. What happens when a subject matter expert creates a powerful model for an algorithm that in turn automatically generates C code that runs too slowly? FPGA experts have created an answer. More and more, the genera... » read more

Introduction To AXI Protocol
By Aldec - 29 Sep, 2016 - Comments: 0

By Brandon Wade When part of a team, your group can become more capable than a single individual, but only if your team can work together and communicate effectively. Having members of a group talk over each other leads to nothing but a cacophony, and nothing gets done. For this reason protocols need to be established, such as letting others speak without interruption, or facing those you ar... » read more

How Cache Coherency Impacts Power, Performance
By Ann Mutschler - 27 Jul, 2016 - Comments: 0

As discussed in part one, one of the reasons cache coherency is becoming more important is the shared common memory resource in designs today. Various agents in the design want to access the data the fastest they can, putting pressure on the CPU complex to manage all of the requests. Until a generation ago, it was okay for the CPU to control that memory and have access to it, as well as be t... » read more

Executive Insight: K. Charles Janac
By Ed Sperling - 24 May, 2016 - Comments: 0

K. Charles Janac, chairman and CEO of Arteris, sat down with Semiconductor Engineering to talk about what's changing in the automotive market, the impact of big data, and heterogeneous cache coherency. What follows are excerpts of that discussion. SE: What are the big changes you're seeing in semiconductor design? Janac: There are a lot of changes right now. Mobility is slowing down and b... » read more

Bridging The IP Divide
By Brian Bailey - 14 Apr, 2016 - Comments: 0

The adoption of an IP-based model has enabled designs to keep filling the available chip area while allowing design time to shrink. But there is a divide between IP providers and IP users. It is an implicit fuzzy contract about how the IP should be used, what capabilities it provides, and the extent of the verification that has been performed. IP vendors have been trying to formalize this as mu... » read more

Coherency, Cache And Configurability
By Ann Mutschler - 24 Mar, 2016 - Comments: 0

Coherency is gaining traction across a wide spectrum of applications as systems vendors begin leveraging heterogeneous computing to improve performance, minimize power, and simplify software development. Coherency is not a new concept, but making it easier to apply has always been a challenge. This is why it has largely been relegated to CPUs with identical processor cores. But the approach ... » read more

Say Hi To Hybrid
By Doug Amos - 29 Oct, 2015 - Comments: 0

It has been proposed for some time that virtual platforms could be linked to emulation hardware in order to co-verify the software and hardware components of an SoC. However, that proposal now has evolved into hybrid emulation, a practical solution to allow pre-silicon verification and validation of today’s complex SoC designs. First-rate work by the standards body Accellera and the Open ... » read more

Blog Review: Dec. 31
By Ed Sperling - 31 Dec, 2014 - Comments: 0

Mentor's J. VanDomelen zeroes in on the two most interesting discoveries from the Philae comet landing. So what was that "eerie cyclical clicking" sound? Synopsys' Ray Varghese digs into basic coherent transaction testing for AXI/ACE compliant interconnects. You might want to put on another pot of coffee. Cadence's Brian Fuller offers some deep insights into synthesis, verification and te... » read more

Reduce Power, Area And Routing Congestion
By Various Writers - 12 Feb, 2014 - Comments: 0

This paper, using an example design, demonstrates how to meet challenging performance, latency and bandwidth goals by using the DesignWare Interconnect Fabric for the ARM® AMBA 3 AXI while minimizing the total area, power consumption and number of top-level wires. The paper also studies the design requirements and examines the optimization features of the DesignWare Interconnect Fabric used to... » read more

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