Temporary Bonding: Enabling the Next Generation of Ultrathin Wafers


Innovative materials are critical for maintaining integrity during advanced semiconductor manufacturing processes. Temporary bonding is being enabled by these new materials and is making a name for itself in the next generation of ultrathin wafer manufacturing. Semiconductor wafers are being forced to become thinner as the push to shrink feature sizes and introduce full-scale 3D integration ... » read more

Surface Modification: Solving Semiconductor Manufacturing Challenges


Process reliability and faster technology deployment are two of the most pressing manufacturing challenges currently facing the semiconductor industry. In a world of ever-evolving technology and innovation, engineers are working to transform materials that don’t possess all the desired functions through a method called “surface modification” – the act of modifying a material’s surface... » read more

The Week In Review: Manufacturing


Trade The trade tensions are building between the U.S. and China. In the latest move, the U.S. Department of Commerce has imposed a ban on U.S. companies selling chips to ZTE, a Chinese telecom equipment and mobile phone vendor. The ban has been implemented on ZTE for seven years after the firm “was caught illegally shipping U.S. goods to Iran,” according to a report from Reuters. This ... » read more

Searching For EUV Defects


Chipmakers hope to insert extreme ultraviolet (EUV) lithography at 7nm and/or 5nm, but several challenges need to be solved before this oft-delayed technology can be used in production. One lingering issue that is becoming more worrisome is how to find defects caused by [gettech id="31045" comment="EUV"] processes. These processes can cause random variations, also known as stochastic effects... » read more

Choosing The Right Interconnect


Efforts to zero in on cheaper advanced packaging approaches that can speed time to market are being sidetracked by a dizzying number of choices. At the center of this frenzy of activity is the [getkc id="36" kc_name="interconnect"]. Current options range from organic, silicon and glass interposers, to bridges that span different die at multiple levels. There also are various fan-out approach... » read more

The Problem With Spin-On Carbon Materials


In an integrated circuit manufacturing process, spin-on-carbon (SOC) materials constitute an important layer for the multilayer process to achieve smaller feature size. The SOC layer responds to the photolithography, pattern transformation, substrate planarization, and a variety of other critical processes. A key challenge in selecting a suitable material is that some processes require a hig... » read more

The Week In Review: Manufacturing


Chipmakers 3D NAND continues to gain steam, but is the industry headed towards a capacity glut in the overall NAND market? Time will tell. In any case, Toshiba is moving forward with its plans to invest in its Fab 6 facility in Japan. The fab will produce the company’s 96-layer 3D NAND devices. Then, Samsung plans to invest $7 billion to double the production capacity for NAND flash memor... » read more

DSA Re-Enters Litho Picture


By Mark LaPedus and Ed Sperling Directed self-assembly (DSA) is moving back onto the patterning radar screen amid ongoing challenges in lithography. Intel continues to have a keen interest in [gettech id="31046" t_name="DSA"], while other chipmakers are taking another hard look at the technology, according to multiple industry sources. DSA isn't like a traditional [getkc id="80" kc_name="... » read more

The Week In Review: Manufacturing


Chipmakers and OEMs After more than four years as chief executive of GlobalFoundries, Sanjay Jha will hand over the company’s top position to Thomas Caulfield, senior vice president and general manager at the foundry vendor. Caulfield, who joined GlobalFoundries in 2014, will become CEO. He has been running the company's fab in New York. "Jha intends to work closely with the company’s shar... » read more

Toward High-End Fan-Outs


Foundries and OSATs are working on more advanced fan-outs, including some with vertically stacked die inside the package, filling a middle ground between lower-cost fan-outs and systems in package on one side and 2.5D and 3D-ICs on the other. These new [getkc id="202" kc_name="fan-outs"] have denser interconnects than previous iterations, and in some cases they include multiple routing layer... » read more

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