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Solving Fan-Out Wafer-Level Warpage Challenges Using Material Science

Improving technologies that enable heterogeneous integration.


Now more than ever we’re finding that semiconductor process engineers are turning to material scientists to help find solutions for their most complex challenges. Currently, they are looking for ways to improve fan-out wafer-level packaging (FOWLP), one of today’s hottest technologies for heterogeneous integration.

Often, with these new advanced solutions come challenges that can impact yields, like die-shift and warpage control. Our material scientists have been investigating a way to optimize the warpage control of a reconstituted wafer and identify material properties that enable fabrication processes for FOWLP.

FOWLP basics
In FOWLP, chips are embedded inside epoxy molding compound (EMC) and then high-density redistribution layers (RDLs) and solder balls are fabricated on the wafer surface to produce a reconstituted wafer.

There are two main approaches to FOWLP, each with advantages and disadvantages. One is die-first FOWLP, in which die can either be placed face up or face down. The other is the RDL-first approach, which can only have face-down assembly.

RDL-first has some distinct advantages over the die-first approach. It achieves high-density RDLs with finer line width/space, offers higher performance, has a larger chip size, can be used for multi-chip integration, and supports panel-level applications. Additionally, the RDL-first approach adapts easily to the conventional flip-chip assembly flow performed at outsourced semiconductor assembly and test service (OSATS) providers.

The process flow
Figure 1 details the RDL-first approach. It starts with a build-up process on a glass wafer that later needs to be debonded. For example, Brewer Science has developed the new BrewerBUILD materials to serve as an all-in-one assist and release layer.

Figure 1: Process flow of the RDL-first fan-out process structure

After the assist and release layer, the RDL fabrication process starts, comprising a titanium/copper (Ti/Cu) seed layer, followed by an under-bump metallization layer (UBM), and the first passivation layer for which we spin-coated curable polymer.

The test device vehicle is comprised of three copper layers (Cu) RDL, which calls for alternating metallization layers with passivation layers. The last wafer-level process is to fabricate 25-μm-diameter microbumps onto the third passivation layer for chip-on-wafer (CoW) bonding.

For CoW bonding, test chips are thinned to 150 µm, the wafer is prelaminated with a non-conductive film (NCF), the wafer is diced, and the chips are bonded to the reconstituted wafer using thermocompression bonding in a flip-chip process. NCF is applied between the chip and wafer to protect microsolder bumps and enhance the structure strength during the subsequent wafer molding. Electrical test results then show a stable connection of microsolder bumps with different bump pitches.

The true test of the assist layer material comes during the debonding step. The thermal stability of the laser release mechanism used can be above 400°C and requires high thermal resistance during wafer-level processing and CoW bonding. After UV-laser scanning, the release mechanism of the assist layer absorbs sufficient laser energy to self-ablate so that it can separate itself from the glass carrier without requiring any additional force.

After debonding and cleaning, solder balls are attached, and the final 10-mm x 10-mm test package is ready for finite element analysis (FEA) for warpage.

Warpage control test
Warpage control of a 300-mm molded wafer is a crucial problem for FOWLP technology development. During our test at Brewer Science, we found that FEA using a 3D model was useful for studying warpage induced by the back-end-of-line (BEOL) wafer-level processes. Moreover, to realize the BEOL process-induced warpage, it was important to consider not only the UBM, passivation, Cu RDL, and sputter Ti/Cu, but also the silicon die, epoxy mold compound (EMC), and glass carrier.

Through simulation, we found that warpage shifted from concave to convex throughout the process flow, due to the coefficient of thermal expansion (CTE) mismatch between the glass carrier and the other materials, including the silicon die.

Overall, warpage increased with a concave profile after Ti/Cu sputter, passivation, RDL and UBM layer fabrication. The warpage trend depended on volume shrinkage of the RDL/passivation fabrication. As wafer molding was finished, warpage increased drastically with a convex profile.

Test key learnings
RDL-first FOWLP has great potential for heterogeneous integration applications. We can now better understand the influence BEOL processes have on FOWLP warpage so that we can learn how to control it. In developing a FEA 3D model, we have added a useful tool to the toolbox that we can use to identify more material properties so that robust package dimensions can be defined.

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