tag: Broadcom

Consolidation And Innovation
By Ed Sperling - 16 Jun, 2015 - Comments: 0

Consolidation is happening across the semiconductor industry, in ways that are very apparent and others that aren't so obvious. On the chipmaker side, NXP's acquisition of Freescale, Avago's acquisition of Broadcom and LSI, and Intel's acquisition of Altera are so big that they require approval by multiple governments. Less obvious are moves such as Apple's build out of its processor team, a... » read more

The Week In Review: Manufacturing
By Mark LaPedus - 12 Jun, 2015 - Comments: 0

Christopher Rolland, an analyst at FBR, made a startling statement in a recent report. “At the pace of consolidation set thus far this year, 32% of all U.S. publicly traded semiconductor companies would be acquired in 2015! While this run-rate is not likely sustainable and should slow as the year progresses, we still expect ~15% consolidation rates for the remainder of this cycle (above low-t... » read more

Avago Buys Broadcom; NXP Spins Off RF Power Unit
By Mark LaPedus - 28 May, 2015 - Comments: 0

Merger and acquisition activity continues to heat up across the semiconductor industry. On one front, Avago Technologies continues on its acquisition spree. And on another front, NXP Semiconductors is moving to spin off its RF power business. And there are other deals in the works as well, including Intel's proposed move to buy Altera. What’s driving the wave of M&A activity? The sem... » read more

M&A Season Now Officially Open
By Ed Sperling - 28 May, 2015 - Comments: 0

A year ago many people were making jokes quite openly about the IoT. It wasn't uncommon to hear quips about the Internet of Nothing, the Internet of Disconnected Things, the Internet of Cars, or some other variant that questioned just how connected everything would become. The tenor of the conversation has changed significantly in the past year. The jokes are fewer, the stakes are higher. An... » read more

Week 49: Are We There Yet?
By Anne Cirkel - 15 May, 2015 - Comments: 0

When I was a little kid my parents would pack me and my sister into the car and drive to the Mediterranean for our summer camping vacation. It was quite a haul from our home on the west side of Germany near the border with Belgium to the south of France, and as is true of any long car trip, the last stretch was the hardest. After hours in the backseat, my sister and I would be craning our necks... » read more

The Week In Review: Design/IoT
By Jesse Allen - 15 May, 2015 - Comments: 0

M&A Avago appears to be on the prowl for a new acquisition. According to a Reuters report, it has made inquiries at Xilinx, Renesas and Maxim and has more than $10B to spend. Avago made a bid for Freescale earlier this year, but NXP ended up buying Freescale for $11.8B. IP Sonics unveiled the ICE-Grain Power Architecture, a power management sub-system for mainstream SoC designs that c... » read more

Layering Protocol Verification
By Synopsys - 22 Apr, 2015 - Comments: 0

Layering protocols are modeled using layering structures that mirror the protocol layers. There are significant challenges in modelling verification components for layering protocols such as (1) reuse, (2) scalability, (3) controllability, and (4)observability. Furthermore, there may be requirements for complex test scenarios where a great deal of interaction is required between test sequence e... » read more

UPF 3.0 Moves Toward Ratification
By Ann Mutschler - 09 Apr, 2015 - Comments: 0

[gettech id="31044" t_name="UPF"] (Unified Power Format) 3.0 — the fourth incarnation in 10 years — is moving closer to the IEEE ballot process. Erich Marschner, verification architect at [getentity id="22017" e_name="Mentor Graphics"] and vice chair of the [gettech id="31043" comment="IEEE 1801"] working group, explained the working group is as close as possible to being on schedule for... » read more

Does Fast Simulation Help Debug Productivity?
By Brian Bailey - 09 Apr, 2015 - Comments: 0

It is nice when a reporter manages to get the scoop of the century, and that was the case at a lunch panel hosted by [getentity id="22032" e_name="Cadence"] at the recent Design and Verification Conference (DVCon) in Santa Clara, CA. Brian Bailey, technology editor for Semiconductor Engineer was the moderator for the panel and broke the news to the crowd. Cadence had developed a logic [getkc id... » read more

Tech Talk: Better Coverage
By Ed Sperling - 08 Apr, 2015 - Comments: 1

Atrenta's Yuan Lu talks about code coverage, functional coverage and the use of assertions in debugging designs. [youtube vid=Hpm-l1z8HTo] » read more

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