tag: Bruker

Why Wafer Bumps Are Suddenly So Important
By Anne Meixner - 10 Aug, 2021 - Comments: 2

Wafer bumps need to be uniform in height to facilitate subsequent manufacturing steps, but a push for 100% inspection in packaging in mission-critical markets is putting a strain on existing measurement technologies. Bump co-planarity is essentially a measure of flatness. Specifically, it measures the variation in bump height, which may have a target, for example, of about 100 microns. As a ... » read more

Residual Stress With EIGER2 R 500K
By Bruker - 10 Aug, 2021 - Comments: 0

Many manufacturing processes leave residual stresses which can affect the performance of manufactured components. Compressive stress can be engineered into a metal coating to resist crack propagation, while tensile stress can be exploited to enhance conductivity in semiconductors. Strained materials exhibit changes in atomic spacing which can be detected by X-ray diffraction (XRD) and related t... » read more

Week In Review: Manufacturing, Test
By Mark LaPedus - 06 Aug, 2021 - Comments: 0

Chipmakers Taiwan’s Foxconn continues to expand its efforts in the semiconductor business. Foxconn has acquired a 6-inch wafer fab and the equipment from Taiwan’s Macronix for NT$2.52 billion (US$90.76 million). With the fab, Foxconn plans to enter the wideband gap semiconductor market, namely silicon carbide (SiC). SiC devices are used in electric vehicles, a market that Foxconn is making... » read more

Chip Shortages Grow For Mature Nodes
By Mark LaPedus - 22 Jul, 2021 - Comments: 0

The current wave of chip shortages is expected to last for the foreseeable future, particularly for a growing list of critical devices produced in mature process nodes. Chips manufactured at mature nodes typically fall under the radar, but they are used in nearly every electronic device, including appliances, cars, computers, displays, industrial equipment, smartphones, and TVs. Many of thes... » read more

IC Data Hot Potato: Who Owns And Manages It?
By SE Staff - 06 Jul, 2021 - Comments: 1

Modern inspection, metrology, and test equipment produces a flood of data during the manufacturing and testing of semiconductors. Now the question is what to do with all of that data. Image resolutions in inspection and metrology have been improving for some time to deal with increased density and smaller features, creating a downstream effect that has largely gone unmanaged. Higher resoluti... » read more

Bumps Vs. Hybrid Bonding For Advanced Packaging
By Mark LaPedus - 23 Jun, 2021 - Comments: 3

Advanced packaging continues to gain steam, but now customers must decide whether to design their next high-end packages using existing interconnect schemes or move to a next-generation, higher-density technology called copper hybrid bonding. The decision is far from simple, and in some cases both technologies may be used. Each technology adds new capabilities in next-generation advanced pac... » read more

Finding, Predicting EUV Stochastic Defects
By Mark LaPedus - 17 Jun, 2021 - Comments: 0

Several vendors are rolling out next-generation inspection systems and software that locates problematic defects in chips caused by processes in extreme ultraviolet (EUV) lithography. Each defect detection technology involves various tradeoffs. But it’s imperative to use one or more of them in the fab. Ultimately, these so-called stochastic-induced defects caused by EUV can impact the perf... » read more

Reliability Costs Becoming Harder To Track
By SE Staff - 08 Jun, 2021 - Comments: 0

Ensuring reliability in chips is becoming more complex and significantly more expensive, shifting left into the design cycle and right into the field. But those costs also are becoming more difficult to define and track, varying greatly from one design to the next based upon process node, package technology, market segment, and which fab or OSAT is used. As the number of options increases fo... » read more

Characterization Of CMP Processes With White Light Interferometry
By Bruker - 08 Jun, 2021 - Comments: 0

Faster computer and electronic processors require smaller features for integrated circuits (IC), which in turn require smaller and smoother substrate surfaces. Chemical mechanical polishing (CMP) has become one of the most critical semiconductor fabrication technologies because it offers a superior means of removing unwanted topography in interlevel dielectric layers and achieving sufficient pl... » read more

The Increasingly Uneven Race To 3nm/2nm
By Mark LaPedus and Ed Sperling - 24 May, 2021 - Comments: 2

Several chipmakers and fabless design houses are racing against each other to develop processes and chips at the next logic nodes in 3nm and 2nm, but putting these technologies into mass production is proving both expensive and difficult. It's also beginning to raise questions about just how quickly those new nodes will be needed and why. Migrating to the next nodes does boost performance an... » read more

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