tag: Bruker

Week In Review: Manufacturing, Test
By Mark LaPedus - 16 Apr, 2021 - Comments: 0

Chipmakers TSMC has posted strong results and raised its capital spending budget to $30 billion, up from its prior guidance of $25 billion to $28 billion in 2021. “Its outlook indicates broad-based semiconductor demand continues to strengthen amid supply chain tightness,” said Weston Twigg, an analyst at KeyBanc, in a research note. “TSMC posted another quarter of strong demand for leadi... » read more

The Quest For Curvilinear Photomasks
By Mark LaPedus - 15 Apr, 2021 - Comments: 1

The semiconductor industry is making noticeable progress on the development of advanced curvilinear photomasks, a technology that has broad implications for chip designs at the most advanced nodes and the ability to manufacture those chips faster and cheaper. The question now is when will this technology move beyond its niche-oriented status and ramp up into high-volume manufacturing. For ye... » read more

Week In Review: Manufacturing, Test
By Mark LaPedus - 02 Apr, 2021 - Comments: 0

Government policy President Biden has rolled out a proposal to boost the infrastructure in the U.S. As part of the plan, the president is calling on Congress to invest $50 billion in U.S. semiconductor manufacturing and research. The proposal must pass Congress, which isn’t going to be easy. “The President’s plan would invest ambitiously in U.S. semiconductor workers, manufacturing, and ... » read more

Week In Review: Manufacturing, Test
By Mark LaPedus - 19 Mar, 2021 - Comments: 0

Chipmakers and OEMs Micron will cease development of 3D XPoint, a next-generation memory technology. Micron also plans to sell a fab that produces 3D XPoint chips. For some time, Intel and Micron have co-developed 3D XPoint, which is based on phase-change memory technology. Intel sells solid-state storage drives (SSDs) using 3D XPoint. In a fab located in Utah, Micron is producing this memo... » read more

EUV Challenges And Unknowns At 3nm and Below
By Mark LaPedus - 19 Nov, 2020 - Comments: 1

The chip industry is preparing for the next phase of extreme ultraviolet (EUV) lithography at 3nm and beyond, but the challenges and unknowns continue to pile up. In R&D, vendors are working on an assortment of new EUV technologies, such as scanners, resists, and masks. These will be necessary to reach future process nodes, but they are more complex and expensive than the current EUV pro... » read more

Speeding Up The R&D Metrology Process
By Mark LaPedus - 16 Jul, 2020 - Comments: 0

Several chipmakers are making some major changes in the characterization/metrology lab, adding more fab-like processes in this group to help speed up chip development times. The characterization/metrology lab, which is generally under the radar, is a group that works with the R&D organization and the fab. The characterization lab is involved in the early analytical work for next-generati... » read more

Metrology Challenges For Gate-All-Around
By Mark LaPedus - 16 Apr, 2020 - Comments: 3

Metrology is proving to be a major challenge for those foundries working on processes for gate-all-around FETs at 3nm and beyond. Metrology is the art of measuring and characterizing structures in devices. Measuring and characterizing structures in devices has become more difficult and expensive at each new node, and the introduction of new types of transistors is making this even harder. Ev... » read more

Making Chips At 3nm And Beyond
By Mark LaPedus and Ed Sperling - 16 Apr, 2020 - Comments: 4

Select foundries are beginning to ramp up their new 5nm processes with 3nm in R&D. The big question is what comes after that. Work is well underway for the 2nm node and beyond, but there are numerous challenges as well as some uncertainty on the horizon. There already are signs that the foundries have pushed out their 3nm production schedules by a few months due to various technical issu... » read more

Week In Review: Manufacturing, Test
By Mark LaPedus - 04 Oct, 2019 - Comments: 0

Packaging and test In a major deal that has some implications in the OSAT supply chain, South Korea’s Nepes has taken over Deca Technologies’ wafer-level packaging manufacturing line in the Philippines. In addition, Nepes has also licensed Deca’s M-Series wafer-level packaging technology. This includes fan-in technology as well as wafer- and panel-level fan-out. It also includes an ad... » read more

Inspection, Metrology Challenges Grow For SiC
By Mark LaPedus - 11 Jun, 2019 - Comments: 2

Inspection and metrology are becoming more critical in the silicon carbide (SiC) industry amid a pressing need to find problematic defects in current and future SiC devices. Finding defects always has been a challenging task for SiC devices. But it’s becoming more imperative to find killer defects and reduce them as SiC device vendors begin to expand their production for the next wave of a... » read more

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