Week In Review: Design, Low Power


Tools & IP Cadence entered the system design and analysis market with the release of Clarity 3D Solver, which creates S-parameter models for use in signal integrity, power integrity, and electromagnetic compliance analysis. The tool uses a distributed adaptive meshing approach for cloud and on-premises distributed computing and it optimized to distribute a job across multiple low-cost comp... » read more

The 7nm Pileup


The number of 7nm designs is exploding. Cadence alone reports 80 new 7nm chips under design. So why now, and what does this all mean? First of all, 7nm appears to be the next 28nm. It's a major node, and it intersects with a number of broad trends that are happening across the industry, all of which involve AI in one way or another. The big question now is how many of them will survive long ... » read more

Spreading Intelligence From The Cloud To The Edge


The challenge of partitioning processing between the edge and the cloud is beginning to come into focus as chipmakers and systems companies wrestle with a massive and rapidly growing volume of data. There are widely different assessments of how much data this ultimately will include, but everyone agrees it is a very large number. Petabytes are simply rounding errors in this equation, and tha... » read more

The Long And Detailed Road To Automotive Compliance


Compliance with automotive safety requirements is slowing down both innovation and participation by a flurry of startups as the whole ecosystem struggles to bring autonomous vehicles to reality. This is particularly onerous for chipmakers, which face a high bar for IC integrity and reliability. They must meet specifications and be free of design errors. Improper behavior in corner-case s... » read more

Blog Review: April 3


Synopsys' Taylor Armerding contends that as the IoT becomes more ubiquitous, the threat of cyber-physical attacks is rising, with the potential for a domino effect if even simple devices are compromised in large enough quantities. Mentor's Colin Walls considers the move away from programming on bare metal with the rise of drivers and RTOSes and when it makes sense to still use the old method... » read more

Big Shift In Multi-Core Design


Hardware and software engineers have a long history of working independently of each other, but that insular behavior is changing in emerging areas such as AI, machine learning and automotive as the emphasis shifts to the system level. As these new markets consume more semiconductor content, they are having a big impact on the overall design process. The starting point in many of these desig... » read more

Week In Review: Design, Low Power


ON Semiconductor will acquire Quantenna Communications for $24.50 per share in an all cash transaction, representing an equity value of approximately $1.07 billion and enterprise value of approximately $936 million. Quantenna, a maker of Wi-Fi chipsets, was founded in 2006 and went public in late 2016. Tools & IP Achronix completed testing and is now demonstrating the 112 Gbps SerDes th... » read more

Digital Twins For Hardware/Software Co-Development


These days it seems like we could play business bingo when watching presentations at conferences, checking off the most keywords mentioned. Hitting the terms AI, ML, IoT, 5G, and edge computing all together almost guarantees your presentation to be a hit. In recent years, the term “digital twin” has gotten a lot of attention. Recent discussions with Brian Bailey and a paper I wrote for GOMA... » read more

Digital Twins Deciphered


Ever since Siemens acquired Mentor Graphics in 2016, a new phrase has become more common in the semiconductor industry – the digital twin. Exactly what that is, and what impact it will have on the semiconductor industry, is less clear. In fact, many in the industry are scratching their heads over the term. The initial reaction is that the industry has been creating what are now termed digi... » read more

Utilizing More Data To Improve Chip Design


Just about every step of the IC tool flow generates some amount of data. But certain steps generate a mind-boggling amount of data, not all of which is of equal value. The challenge is figuring out what's important for which parts of the design flow. That determines what to extract and loop back to engineers, and when that needs to be done in order to improve the reliability of increasingly com... » read more

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