中文 English

Week In Review: Design, Low Power

Electromagnetic simulation; startup predicts failures in chips; Intel’s new FPGA.

popularity

Tools & IP
Cadence entered the system design and analysis market with the release of Clarity 3D Solver, which creates S-parameter models for use in signal integrity, power integrity, and electromagnetic compliance analysis. The tool uses a distributed adaptive meshing approach for cloud and on-premises distributed computing and it optimized to distribute a job across multiple low-cost computers while remaining equally efficient when running on more powerful servers, and the company says it is 10X faster than legacy 3D field solvers while maintaining accuracy. Integration with other Cadence tools allows merging of mechanical structures such as cables and connectors with the system design to model the electrical-mechanical interconnect as a single model.

Cadence also added to its cloud portfolio with CloudBurst, a platform for hybrid cloud environments that provides access to pre-installed Cadence design tools in a ready-to-use cloud environment built on either Amazon Web Services (AWS) or Microsoft Azure. The company says the offering allows for scalability to address the peak requirements of design projects with deployment within a day or two of purchase, rather than weeks for internally provided cloud solutions.

Aldec released the latest version of its unified requirements lifecycle management EDA tool. New features in Spec-TRACER focus on to better support for team-based projects working on designs that must be certified to safety standards with the addition of a relational database, CSV parser for capturing traceability data from more source documents, Aldec Coverage Database (ACDB) parser for capturing the verification plan together with coverage results, and an IBM DOORS parser for capturing traceability links and hierarchical relationships.

Intel launched a new family of FPGAs. Agilex FPGA is built on Intel’s 10nm process with heterogeneous 3D SiP technology and supports the Compute Express Link cache and memory coherent interconnect, hardened BFLOAT16 and up to 40 teraflops of DSP performance, and up to 40% higher performance or 40% lower total power compared with Stratix 10 FPGAs. The new family targets embedded, network and data-center markets.

Deals
Horizon Robotics licensed Arteris IP’s FlexNoC Interconnect for use in multiple ADAS chips. Horizon cited the ability to optimize and implement chip architectures for ideal dataflow within ADAS systems to ensure processing elements avoid starvation and communications occur with minimum latency.

Cadence’s Innovus Implementation System and Quantus Extraction Solution are now enabled for Samsung Foundry’s Gate-All-Around (GAA) technology. The two companies also completed a test vehicle tapeout using EUV technology.

Numbers
Startup proteanTecs emerged from stealth mode after completing a Series B financing round of $35 million. The company’s focus is prediction of failures in electronics using inferred measurements for chip health and performance monitoring, a system it calls Universal Chip Telemetry. “We offer a one-stop cloud-based platform, that combines data derived from proprietary Agents embedded in chips, with machine learning and data analytics,” said Shai Cohen, proteanTecs’ co-founder and CEO. “This significantly improves chip and system production quality, while tracking operational reliability and alerting on faults before they become failures.” The Israel-based company’s three founders were also co-founders of Mellanox. In total, proteanTecs has raised nearly $50 million to date from investors including Avigdor Willenz, Intel Capital, ITI Venture Capital Partners, Mitsubishi UFJ Capital, Redline Capital Management S.A., Viola Ventures, WRVI Capital, Zeev Ventures and others. The company says its technology is already being used by a range of customers.

Movellus raised $6 million in Series A venture funding. The startup’s focus is automating the generation of traditional analog IP using digital tools and standard cells with an initial product line of PLLs, DLLs & LDOs that are optimized per design for markets ranging from edge AI to cloud computing. The round was led by Stata Venture Partners, with participation from Intel Capital and University of Michigan’s MINTS and brings the company’s funding to $10 million. Movellus will use the funds to expand infrastructure, expand its product portfolio, and increase market penetration.

AI startup SambaNova Systems completed a $150 million Series B funding round. The company is working on a systems platform for running AI applications using a software-defined hardware strategy that enables software and algorithms to define processing power and dataflow requirements. The round was led by Intel Capital, with additional participation from existing investors GV (formerly Google Ventures), Walden International, Atlantic Bridge Ventures, and Redline Capital. The financing will be used to extend SambaNova’s product roadmap and expand the software capabilities of its products.

Events
Fireside Chat with Paul Cunningham: April 10, 6:30-9:00 p.m. in Milpitas, CA. Jim Hogan and Cadence’s Paul Cunningham will discuss topics from the startup experience, artificial intelligence, concurrent physical optimization to system functional verification and open source architectures. The event is hosted by the ESD Alliance.

Linley Spring Processor Conference 2019: April 10-11 in Santa Clara, CA. Beginning with an overview of the processor and IP market, technologies, equipment-design, and silicon trends, the event will include talks and panel discussions on a range of topics. AI chips and IoT security are both major focuses.

DAC 2019: June 2-6 in Las Vegas, NV. The conference and exhibition includes a range of tracks, including last year’s addition of machine learning/AI. On the show floor, the Design Infrastructure Alley will return for a second year. Free registration is now open to attend the exhibits and keynotes, sponsored by Avatar Integrated Systems, ClioSoft and Truechip.

ES Design West: July 9-11 in San Francisco, CA. The new conference focuses on IP, EDA, embedded software, design services, and infrastructure. Along with a dedicated conference track, there will be presentations and panels on the show floor. Presented by the ESD Alliance, the conference is co-located with SEMICON West. Super-early registration ends Mar. 29.



Leave a Reply


(Note: This name will be displayed publicly)