Week In Review: Design, Low Power


Silicon Labs will acquire Redpine Signals' Wi-Fi and Bluetooth business, development center in Hyderabad, India, and extensive patent portfolio for $308 million in cash. Silicon Labs says the acquisition will expand the company's IoT wireless technology, including smart phone and industrial IoT, and accelerate its roadmap for Wi-Fi 6. The deal is expected to close in the second quarter of 2020.... » read more

Week In Review: Auto, Security, Pervasive Computing


National Instruments is offering free online training courses to anyone anywhere, until the end of April to help support the engineering community during COVID-19 crisis. Some instructor-led virtual training is available at reduced cost. NIWeek has been postponed this year until August 3-5, 2020. Click here for more news about how the semiconductor industry is handling COVID-19. AI, machi... » read more

Blog Review: March 18


Arm's Divya Prasad investigates whether power rails that are buried below the BEOL metal stack and back-side power delivery can help alleviate some of the major physical design challenges facing 3nm nodes and beyond. Rambus' Steven Woo takes a look at a Roofline model for analyzing machine learning applications that illustrates how AI applications perform on Google’s tensor processing unit... » read more

HBM Issues In AI Systems


All systems face limitations, and as one limitation is removed, another is revealed that had remained hidden. It is highly likely that this game of Whac-A-Mole will play out in AI systems that employ high-bandwidth memory (HBM). Most systems are limited by memory bandwidth. Compute systems in general have maintained an increase in memory interface performance that barely matches the gains in... » read more

Week In Review: Design, Low Power


Tools & IP Synopsys revealed DSO.ai (Design Space Optimization AI), an autonomous AI application that searches for optimization targets in very large solution spaces of chip design, inspired by the process of DeepMind's game-playing AlphaZero. DSO.ai engines ingest large data streams generated by chip design tools and use them to explore search spaces, observing how a design evolves over t... » read more

Week In Review: Auto, Security, Pervasive Computing


AI, machine learning Cadence says it has optimized its Tensilica HiFi digital signal processor IP to efficiently execute TensorFlow Lite for Microcontrollers, which are used in Google’s machine learning platform for edge. This means developers of AI/ML on the edge systems can now put better audio processing on edge devices with ML applications like keyword detection, audio scene detection, n... » read more

Demystifying Mirror Types


I’m not talking about carnival funhouse mirrors, but rather the different options for mirroring symbols, vias, and bond fingers in your IC Package layout. The Allegro Package Designer Plus and SiP Layout tools have two distinct styles of mirroring which are used in different places. Often, I get questions about what, exactly, those differences are. And even more, why the styles are used for d... » read more

Power Challenges In ML Processors


The design of artificial intelligence (AI) chips or machine learning (ML) systems requires that designers and architects use every trick in the book and then learn some new ones if they are to be successful. Call it style, call it architecture, there are some designs that are just better than others. When it comes to power, there are plenty of ways that small changes can make large differences.... » read more

Blog Review: Mar. 11


Rambus' Steven Woo examines how the upcoming deployment of 5G will enable processing at the edge, and how the edge is getting refined further into the near edge and the far edge with a range of AI solutions across it. A Synopsys writer explains the types of Compute Express Link devices and CXL's unique verification challenges like maintaining the cache coherency between a host CPU and an acc... » read more

System-Level Electro-Thermal Analysis of RDS(ON) for Power MOSFET


Authors: Rajen Murugan1, Nathan Ai2, and C.T. Kao2 1 Texas Instruments, Inc., Dallas, Texas, 75044, USA 2 Cadence Design Systems, Santa Clara, California, USA A coupled-electro-thermal RDS(ON) (drain to source ON resistance) co-analysis methodology for Power MOSFET is proposed. The methodology contains two functional modules: 1) physical field solvers and 2) equivalent circuit/network so... » read more

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