tag: Cadence

Connected Cars: From Chip To City
By Ann Mutschler - 01 Nov, 2018 - Comments: 0

As the automotive industry moves closer to autonomous vehicles, ecosystem players are focusing on the infrastructure pieces needed to make autonomous technology a reality for the first adopters, which are most likely commercial fleets. Vehicle-to-infrastructure (V2I or v2i) is a communications model that allows vehicles to share information with the components that support a country's hi... » read more

Blog Review: Oct. 31
By Jesse Allen - 31 Oct, 2018 - Comments: 0

Mentor's Joe Hupcey III digs into handling memories effectively with formal through abstraction and the easiest ways to address memory-related inconclusive results. Cadence's Paul McLellan explains DARPA's CHIPS program that aims to lower semiconductor design costs through chiplet-based designs, the current status of the work, and what the next steps will be. Synopsys' Sangeeta Kulkarni c... » read more

The Impact of Domain Crossing on Safety
By Brian Bailey - 31 Oct, 2018 - Comments: 0

Semiconductor Engineering sat down to discuss problems associated with domain crossings with Alex Gnusin, design verification technologist for Aldec; Pete Hardee, director, product management for Cadence; Joe Hupcey, product manager and verification product technologist for Mentor, a Siemens Business; Sven Beyer, product manager design verification for OneSpin; and Godwin Maben, applications en... » read more

The Impact of Moore’s Law Ending
By Brian Bailey - 29 Oct, 2018 - Comments: 2

Over the past couple of process nodes the chip industry has come to grips with the fact that Moore's Law is slowing down or ending for many market segments. What isn't clear is what comes next, because even if chipmakers stay at older nodes they will face a series of new challenges that will drive up costs and increase design complexity. Chip design has faced a number of hurdles just to get ... » read more

Week In Review: Design, Low Power
By Jesse Allen - 26 Oct, 2018 - Comments: 0

Tools OneSpin launched a formal verification tool that integrates with all major simulators, coverage databases and viewers, and chip design verification planning tools to provide a comprehensive view of verification progress. Comprised of two new formal apps, it can identify unreachable coverage points and provide them to the simulator to reduce wasted effort. Synopsys released the latest ... » read more

The Race To Design Larger Systems
By Ed Sperling - 25 Oct, 2018 - Comments: 0

For more than a decade, tools vendors and design houses have been talking about leveraging their tools and expertise to help design systems of systems. They're finally getting their chance. The basic idea behind this strategy has always been that issues inside any electronic system—performance, power, signal integrity, area—have all been dealt all the way down to the sub-atomic level in ... » read more

What Makes A Good AI Accelerator
By Ann Mutschler - 25 Oct, 2018 - Comments: 3

The rapid growth and dynamic nature of AI and machine learning algorithms is sparking a rush to develop accelerators that can be optimized for different types of data. Where one general-purpose processor was considered sufficient in the past, there are now dozens vying for a slice of the market. As with any optimized system, architecting an accelerator — which is now the main processing en... » read more

EDA Cloud Adoption Hits Speed Bumps
By Brian Bailey - 25 Oct, 2018 - Comments: 0

If moving semiconductor design to the Cloud was easy and beneficial, everyone would be doing it. But so far, few have done more than dip a toe. The level of difficulty associated with migrating to the Cloud varies, depending upon who you talk to. The reality is that not everyone makes it as easy as it could be, or is not willing to put the necessary effort into making it easier. There is cer... » read more

The Power Of Ecosystems At Arm TechCon 2018
By Frank Schirrmeister - 25 Oct, 2018 - Comments: 0

I have long been fascinated by the workings of ecosystems. Last week’s Arm TechCon in San Jose was a textbook example of how ecosystems work, overlap and how the electronics development work is indeed like a village—it takes many players to make things happen to enable end users to receive the latest gadgets like phones, fitness trackers, electronic watches, etc. The game of electronic ecos... » read more

A Method to Measure Die Pad Capacitance
By Cadence - 24 Oct, 2018 - Comments: 0

This paper defines a method to measure the chip die pad capacitance using time delay reflectometry (TDR). This method is useful for measuring the low-value capacitance that is present at the end of a transmission line. In all protocol specifications, pad capacitance is an important electrical parameter to be measured because it directly affects the bandwidth. However, it is a challenge to me... » read more

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