Speeding Up 3D Design


2.5D and 3D designs have garnered a lot of attention recently, but when should these solutions be considered and what are the dangers associated with them? Each new packaging option trades off one set of constraints and problems for a different set, and in some cases the gains may not be worth it. For other applications, they have no choice. The tooling in place today makes it possible to de... » read more

Power Complexity On The Rise


New chip architectures and custom applications are adding significant challenges to chip design and verification, and the problems are becoming much more complex as low power is added into the mix. Power always has been a consideration in design, but in the past it typically involved different power domains that were either on, off, or in some level of sleep mode. As hardware architectures s... » read more

Blog Review: Nov. 13


Applied Materials' Buvna Ayyagari-Sangamalli argues that the siloed structure that produced the computing eras of the past will not be sufficient to fuel the AI era and that a new codesign approach to everything from architecture to materials is needed. Arm's Wendy Elsasser examines emerging non-volatile memories and how they have triggered innovation for new memory protocols and optimized s... » read more

Leveraging Data In Chipmaking


John Kibarian, president and CEO of PDF Solutions, sat down with Semiconductor Engineering to talk about the impact of data analytics on everything from yield and reliability to the inner structure of organizations, how the cloud and edge will work together, and where the big threats are in the future. SE: When did you recognize that data would be so critical to hardware design and manufact... » read more

Week In Review: Design, Low Power


Cadence unveiled a static timing/signal integrity analysis and power integrity analysis tool, Tempus Power Integrity Solution, that integrates the Tempus Timing Signoff and Voltus IC Power Integrity signoff engines. Early use cases demonstrated it correctly identified IR drop errors, avoiding silicon failure prior to tapeout and improving the maximum frequency in silicon by up to 10%. Arasan... » read more

Week in Review: Iot, Security, Automotive


IoT STMicroelectronics is now supporting LoRaWAN firmware updates over the air (FUOTA) in the STM32Cube ecosystem. Microsoft is adding ANSYS Twin Builder to its Microsoft Azure Digital Twins software, which companies use to create digital twins of machinery and IoT devices that are deployed in remotely. The digital replica of actual devices helps companies predict when maintenance is needed... » read more

Technological Dead Ends


Sometimes something comes along that looks like it is a portent of things to come, but then turns out to be a technological dead end. For example, in the 1990s, it seemed that you couldn't go to the mailbox or rent a video without getting an AOL CD offering a free trial. They were even in some cereal boxes. It was the era of the 56Kb dialup modem, and AOL's walled garden was king as everyone we... » read more

Blog Review: Nov. 6


Cadence's Paul McLellan considers why high-performance compute, high-performance networks, and security will all be vital to the next wave of devices and the importance of optimization. Synopsys' Taylor Armerding points to some best practices for assessing your supply chain to find the weak links that could lead to a security breach, from why to make it a priority to what to ask software ven... » read more

Simultaneous Localization And Mapping


Amol Borkar, senior product manager at Cadence, explains how to track the movement of an object in a scene and how to match features from one image to the next using SLAM. The technology is used in everything from mobile phones to automotive and drones. » read more

Service Revenue Growing With Chip Complexity


Rising complexity, new markets, and a shortage of in-house expertise are beginning to rekindle demand for services for the first time in nearly a decade. The semiconductor industry has been racing to design chips for a variety of new and existing applications, but they are facing challenges on a number of fronts: Leading-edge chips require new architectures due to a sharp reduction in s... » read more

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