tag: Cadence

Blog Review: Aug. 1
By Jesse Allen - 01 Aug, 2018 - Comments: 0

Synopsys' Taylor Armerding explains the recent cyberattack on Singapore's largest healthcare group, SingHealth. The "well-planned" attack compromised the personal information of about a quarter of the country's population, including Prime Minister Lee Hsien Loong. Cadence's Paul McLellan looks at the factors that make China's automotive market much different from the rest of the world and th... » read more

Why Parallelization Is So Hard
By Brian Bailey - 30 Jul, 2018 - Comments: 2

Semiconductor Engineering sat down to talk about parallelization efforts within EDA with Andrea Casotto, chief scientist for Altair; Adam Sherer, product management group director in the System & Verification Group of Cadence; Harry Foster, chief scientist for Mentor, a Siemens Business; Vladislav Palfy, global manager for applications engineering at OneSpin; Vigyan Singhal, chief Oski for ... » read more

Week In Review: Design, Low Power
By Jesse Allen - 27 Jul, 2018 - Comments: 0

Tools & IP Cadence uncorked the latest version of the Sigrity signal integrity analysis family of tools, adding a 3D design and 3D analysis environment integrated with Allegro PCB tools that allows users to import mechanical structures, such as cables and connectors, and merge them with the PCB for modeling and optimization as one structure. It also adds full Rigid-Flex PCB extraction from... » read more

The Future Is Bright: DARPA Is Driving Electronic Resurgence
By Frank Schirrmeister - 26 Jul, 2018 - Comments: 0

This week, DARPA ran the Electronics Resurgence Initiative (ERI) Summit in San Francisco, and while we are certainly staring at some daunting challenges to continue the fast-paced development in electronics, it looks like the future actually looks quite bright. I found myself whistling, “How lucky we are to be alive right now” from Lin-Manuel Miranda’s Hamilton when leaving the stunning P... » read more

Debug Issues Grow At New Nodes
By Ann Mutschler - 26 Jul, 2018 - Comments: 0

Debugging and testing chips is becoming more time-consuming, more complicated, and significantly more difficult at advanced nodes as well as in advanced packages. The main problem is that there are so many puzzle pieces, and so many different use cases and demands on those pieces, that it's difficult to keep track of all the changes and potential interactions. Some blocks are "on" sometimes,... » read more

When Bugs Escape
By Brian Bailey - 26 Jul, 2018 - Comments: 0

Bugs are a fact of life, and they always have been. But verification methodologies may not have evolved fast enough to keep up with the growing size and complexity of systems. The types of bugs are changing, too. Some people call these corner cases. Others call them outliers. Still another group refers to them as simulation-resistance superbugs. In markets such as automotive, the notion o... » read more

Where ML Works Best
By Ed Sperling - 26 Jul, 2018 - Comments: 0

Anirudh Devgan, president of Cadence, sat down with Semiconductor Engineering to discuss machine learning inside and outside of EDA tools and how that will affect the future of chip and system design. What follows are excerpts of that discussion. SE: How do you see the market and use of machine learning shaping up? Devgan: There are three main areas—machine learning inside, machine lear... » read more

Blog Review: July 25
By Jesse Allen - 25 Jul, 2018 - Comments: 0

Mentor's Daniel Clarke takes a look at some of the challenges to effective sensor fusion in automotive and why it's important to develop different sensing methodologies for particular driving tasks and levels of automation. Cadence's Meera Collier explains the evolution in wireless networks that's brought us to 5G and why it will be such a big deal for a massively connected world. Synopsy... » read more

Verification As A Flow (Part 3)
By Brian Bailey - 24 Jul, 2018 - Comments: 0

Semiconductor Engineering sat down to discuss the transformation of verification from a tool to a flow with Vladislav Palfy, global manager application engineering for OneSpin Solutions; Dave Kelf, chief marketing officer for Breker Verification Systems; Mark Olen, product marketing group manager for Mentor, A Siemens Business; Larry Melling, product management director, System & Verificati... » read more

Blog Review: July 18
By Jesse Allen - 18 Jul, 2018 - Comments: 0

Synopsys' Shivani Bansal introduces DFI 5.0, the latest interface specification that defines signals, timing, and functionality required for efficient communication between the memory controller and PHY, including changes to boost performance in DDR5/LPDDR5. Mentor's Ricardo Anguiano contends that for greater autonomy in vehicles, centralized sensor fusion is necessary to both reduce the cos... » read more

← Older posts Newer posts →

  • Sponsors

About

Navigation

Connect With Us

Copyright ©2013-2025 SMG   |  Terms of Service  |  Privacy Policy