tag: Cadence

AI For Circuit Design Quality, Productivity, And Advanced-Node Mapping
By Steve Brown - 26 Oct, 2023 - Comments: 0

The future of circuit design, encompassing analog, RF/5G, and custom electronic circuits, is set to be revolutionized by the integration of generative AI tools. These advanced tools will not only enhance the quality of designs and boost designer productivity but also facilitate the mapping of designs from older semiconductor process nodes to more advanced nodes such as 3nm and below. This blog ... » read more

Navigating EDA Vendor Cloud Options
By Ann Mutschler - 25 Oct, 2023 - Comments: 0

Experts at the Table: Semiconductor Engineering sat down to discuss the challenges of cost-dependent cloud decisions, and how to navigate between different EDA vendor clouds options with Philip Steinke, fellow, CAD infrastructure and physical design at AMD; Mahesh Turaga, vice president of business development for cloud at Cadence Design Systems; Richard Ho, vice president hardware engineering ... » read more

Blog Review: October 25
By Jesse Allen - 25 Oct, 2023 - Comments: 0

Synopsys’ Graham Allan looks at enhancements in the LPDDR5X standard, such as a speed increase from 6.4Gbps to 8.5Gbps using the same 1.1V core voltage as LPDDR5 alongside better signal integrity, reliability, and battery efficiency. Cadence’s Krunal Patel examines the essential components and operation of MACsec, a security protocol to ensure the confidentiality and integrity of data tr... » read more

Why A DSP Is Indispensable In The New World of AI
By Cadence - 25 Oct, 2023 - Comments: 0

Chips being designed today for the automotive, mobile handset, AI-IoT (artificial intelligence - Internet of things), and other AI applications will be fabricated in a year or two, designed into end products that will hit the market in three or more years, and then have a product lifecycle of at least five years. These chips will be used in systems with a large number and various types of senso... » read more

Chip Industry Week In Review
By The SE Staff - 20 Oct, 2023 - Comments: 0

By Susan Rambo, Gregory Haley, and Liz Allan SRC unfurled its Microelectronics and Advanced Packaging (MAPT) industry-wide 3D semiconductor roadmap, addressing such topics as advanced packaging, heterogeneous integration, analog and mixed-signal semiconductors, energy efficiency, security, the related foundational ecosystem, and more. The guidance is the collective effort of 300 individuals ... » read more

Heterogeneous Integration Finding Its Footing
By Ed Sperling - 19 Oct, 2023 - Comments: 0

Semiconductor Engineering sat down to discuss heterogeneous integration with Dick Otte, president and CEO of Promex Industries; Mike Kelly, vice president of chiplets/FCBGA integration at Amkor Technology; Shekhar Kapoor, senior director of product management at Synopsys; John Park, product management group director in Cadence's Custom IC & PCB Group; and Tony Mastroianni, advanced packagin... » read more

Blog Review: October 18
By Jesse Allen - 18 Oct, 2023 - Comments: 0

Siemens' Stephen Chavez suggests including analog mixed signal analysis and board level parasitics within the design process from the earliest electrical design stage and throughout final release of the PCB design. Synopsys’ Filip Thoen, Leonard Drucker, and Vivek Prasad highlight how the complexities and interdependencies of multi-die systems create new challenges for software bring-up, a... » read more

Chip Industry Talent Shortage Drives Academic Partnerships
By Liz Allan - 16 Oct, 2023 - Comments: 0

Universities around the world are forming partnerships with semiconductor companies and governments to help fill open and future positions, to keep curricula current and relevant, and to update and expand skills for working engineers. Talent shortages repeatedly have been cited as the number one challenge for the chip industry. Behind those concerns are several key drivers, and many more dom... » read more

Chip Industry Week In Review
By The SE Staff - 13 Oct, 2023 - Comments: 0

By Liz Allan, Jesse Allen, and Karen Heyman. Canon uncorked a nanoimprint lithography system, which the company said will be useful down to about the 5nm node. Unlike traditional lithography equipment, which projects a pattern onto a resist, nanoimprint directly transfers images onto substrates using a master stamp patterned by an e-beam system. The technology has a number of limitations and... » read more

Partitioning Processors For AI Workloads
By Ann Mutschler - 12 Oct, 2023 - Comments: 0

Partitioning in complex chips is beginning to resemble a high-stakes guessing game, where choices need to extrapolate from what is known today to what is expected by the time a chip finally ships. Partitioning of workloads used to be a straightforward task, although not necessarily a simple one. It depended on how a device was expected to be used, the various compute, storage and data paths ... » read more

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