tag: Cadence

Calculating Emulation’s Complex Cost Of Ownership
By Ed Sperling - 25 Oct, 2012 - Comments: 0

By Ann Steffora Mutschler Hardware emulation or hardware-assisted verification –whichever term you choose—has been around for decades. But until recently it has seen only modest adoption due to the high cost, long set-up time, power and IT requirements, among other things. But with simulation running out of steam between 50 and 100 million gates, this specialized hardware makes a ... » read more

Optimizing And Maintaining A High-Performing Design Environment
By Various Writers - 25 Oct, 2012 - Comments: 0

To maximize your investment in electronic design automation (EDA) tools, your infrastructure and processes must be optimized for growing and frequently changing design needs. Cadence Client Technology Solutions is dedicated to enhancing EDA tool performance, ensuring stability, and removing critical bottlenecks. Through close collaboration with hundreds of customers worldwide, we have unique in... » read more

The Complexity Of System Development And Verification
By Frank Schirrmeister - 23 Oct, 2012 - Comments: 1

By Frank Schirrmeister The electronics industry is undergoing a fast transition towards new paradigms for system development and verification as traditional development methods reach their breaking points. Developing a system development and verification environment can become a costly undertaking, and can involve many direct and sometimes even more hidden cost. To understand the cost aspects,... » read more

Transitioning States
By Ed Sperling - 11 Oct, 2012 - Comments: 0

By Ann Steffora Mutschler While the concept of finite state machines is mature, understanding their role in design, the transitions between them and how to verify them are fundamental to managing power in today’s large SoCs. In essence, a finite state machine is a set of inputs and outputs and gate bits that describes the operation of the system. “Transitions happen from one state to... » read more

Design For Power
By Ed Sperling - 11 Oct, 2012 - Comments: 0

By Ed Sperling Figuring out a single power budget and mapping out what has become known as holistic power intent for an SoC sounds great on paper, but reality has turned out to be somewhat different. While system architects still call the shots on how a chip is designed, there is a lot more information flowing in all directions further down the design chain these days. Unlike functionality,... » read more

CPU Architectures Get Specific
By Ed Sperling - 11 Oct, 2012 - Comments: 0

By Ann Steffora Mutschler SoC and system design is already complicated, but as complexity continues to rise the industry must determine how to maintain sensitivity to power and cost and performance in the CPU architecture. Where does this stand today—not just with architectures and microarchitectures for consumer electronics but all other kinds of applications? What kinds of changes... » read more

The Increasing Challenge Of Reducing Latency
By Ed Sperling - 11 Oct, 2012 - Comments: 0

By Ed Sperling When the first mainframe computers were introduced the big challenge was to improve performance by decreasing the latency between spinning reels of tape and the processor—while also increasing the speed at which the processor could crunch ones and zeroes. Fast forward more than six decades and the two issues are now blurred and often confused. Latency is still a drag on per... » read more

LP Test
By Luke Lang - 11 Oct, 2012 - Comments: 0

By Luke Lang Last month, we discussed testing a portion of a chip at a time to reduce overall power dissipation during test. However, this does not address local power dissipation hotspots that can cause excessive IR drop. These hotspots can occur in regions where many nets are switching at the same time. Typically, a chip’s power grid is designed to meet IR drop specification in the func... » read more

Experts at the Table: Black Belt Power Management
By Ann Mutschler - 11 Oct, 2012 - Comments: 0

By Ann Steffora Mutschler Low-Power/High-Performance Engineering sat down to discuss rising integration challenges caused by an increasing amount of black-box IP with Qi Wang, technical marketing group director, solutions marketing, for the low-power and mixed-signal group at Cadence; J. Bhasker, architect at eSilicon Corp.; Navraj Nandra, senior director of product marketing for analog an... » read more

Thanks For The Memories
By Ed Sperling - 27 Sep, 2012 - Comments: 0

By Ed Sperling The amount of real estate in a design now devoted to memories—SRAM on chip, DRAM off chip, and a few other more exotic options showing up occasionally—is a testament to the amount of data that needs to be utilized quickly in both mobile and fixed devices. Memory is almost singlehandedly responsible for the routing congestion now plaguing complex SoCs. It is one of the mai... » read more

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