Experts at the Table: Stacking the Deck


By Ann Steffora Mutschler System-Level Design sat down to discuss challenges to 3D-IC adoption with Samta Bansal, product marketing for applied silicon realization in strategy and market development at Cadence; Carey Robertson, product marketing director at Mentor Graphics; Karthik Chandrasekar, member of technical staff in IC Design at Altera; and Herb Reiter, president of EDA2ASIC Consulting... » read more

Best Practices In Verification


By Ann Steffora Mutschler The advent of advanced verification methodologies such as the UVM and its predecessors VMM and OVM has changed the verification landscape in many ways. Design and verification teams used to worry about simulator performance (i.e., how fast the simulator runs a particular test case), but the introduction of constrained-random stimulus and functional coverage and associ... » read more

Interface Additions To The e Language For Effective Communication With SystemC TLM 2.0 Models


The last several years have seen strong adoption of transaction-level models using SystemC TLM 2.0. Those models are used for software validation and virtual prototyping. For functional verification, TLMs have a number of advantages—they are available earlier, they allow usersto divide their focus on verifying functionality and protocol/timing details, they enable higher level reuse, and they... » read more

Yikes! Why Is My SystemVerilog Testbench So Slooooow?


It turns out that [gettech id="31023" comment="SystemVerilog"] != [gettech id="31017" comment="verilog"]. OK, we all figured that out a few years ago as we started to build verification environments using [gettech id="31026" comment="IEEE 1800"] SystemVerilog. While it did add design features like new ways to interface code, it also had verification features like classes, dynamic data types, ... » read more

The Seven Layers Of Hardware-Software Debug


By Frank Schirrmeister [caption id="attachment_9863" align="alignnone" width="639"] Seven Layers of Hardware/Software Debug[/caption] Of course I will be in trouble once this blog is posted. This post is about hardware/software debug,  and I tried to layer a set of different levels for the scope and applicability of debug. I counted seven layers, but I am sure that one may be able to arr... » read more

Experts At The Table: Coherency


System-Level Design sat down to discuss coherency with Mirit Fromovich, principal solutions engineer at Cadence; Drew Wingard, CTO of Sonics; Mike Gianfagna, vice president of marketing at Atrenta, and Marcello Coppola, technical director at STMicroelectronics. What follow are excerpts of that conversation. SLD: We’ve been hearing a lot about Wide I/O. Why is it so important and what effec... » read more

Experts At The Table: Coherency


System-Level Design sat down to discuss coherency with Mirit Fromovich, principal solutions engineer at Cadence; Drew Wingard, CTO of Sonics; Mike Gianfagna, vice president of marketing at Atrenta, and Marcello Coppola, technical director at STMicroelectronics. What follow are excerpts of that conversation. SLD: We’ve been hearing a lot about Wide I/O. Why is it so important and what effec... » read more

Experts At The Table: Challenges At 20nm


By Ed Sperling Low-Power/High-Performance Engineering sat down to discuss the challenges at 20nm and beyond with Jean-Pierre Geronimi, special projects director at STMicroelectronics; Pete McCrorie, director of product marketing for silicon realization at Cadence; Carey Robertson, director of product marketing at Mentor Graphics; and Isadore Katz, president and CEO of CLK Design Automation. Wh... » read more

Experts At The Table: Challenges At 20nm


By Ed Sperling Low-Power/High-Performance Engineering sat down to discuss the challenges at 20nm and beyond with Jean-Pierre Geronimi, special projects director at STMicroelectronics; Pete McCrorie, director of product marketing for silicon realization at Cadence; Carey Robertson, director of product marketing at Mentor Graphics; and Isadore Katz, president and CEO of CLK Design Automation. Wh... » read more

3D-IC Impact On Computational Lithography?


While 3D devices and technology such as through-silicon vias (TSVs) definitely complicate matters in the design, verification and manufacturing space, one might assume there would also be an impact on the computational lithography tools that are used to ensure printability. Have no fear. Industry experts assure us that this is not the case. Lithography expert Chris Mack acknowledged that ... » read more

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