tag: Cadence

Blog Review: Dec. 4
By Ed Sperling - 04 Dec, 2013 - Comments: 0

Mentor’s Harry Foster closes his epic study on functional verification with an interesting insight about the real value of industry studies—new questions. It’s hard to argue with that. Cadence’s Brian Fuller takes a shot at the people taking shots at Amazon’s drone delivery service (the term du jour is robots). It does sound cool, as long as they don’t deliver the kind of payloa... » read more

How To Achieve 10X Faster Power Integrity Analysis And Signoff
By Various Writers - 04 Dec, 2013 - Comments: 0

In our mobile computing era, system-on-chip (SoC) design has become much more complex, with challenges from complex design rules on advanced process nodes, low-power circuitry design techniques, and increasing circuit sizes. Power integrity is a crucial part of successful design signoff. This paper discusses a new tool that speeds power integrity analysis and signoff by 10X compared to other te... » read more

Blog Review: Nov. 27
By Ed Sperling - 27 Nov, 2013 - Comments: 0

Synopsys’ Brent Gregory is looking at real-world experiments to figure out which EDA software is better. Make sure to check out his stats. Cadence’s Brian Fuller interviews two Samsung engineers in a video about the image technology in smart phone cameras and just how far it’s progressed. Hint: Don’t forget to charge your phone on your next vacation. Mentor’s Colin Walls points ... » read more

The Week In Review: System-Level Design
By Ed Sperling - 22 Nov, 2013 - Comments: 0

Synopsys rolled out new non-volatile memory IP that cuts power by 90% and reduces area in half. The company said it accomplished this feat with a single-bit read capability, which can drop read operation down to 0.9 volts and peak current to less than 10 microamps during erase and programming. The target of the ultra-low power IP is RFID and near-field computing ICs. Mentor Graphics posted p... » read more

Even Standard IP Isn’t Always Standard
By Ed Sperling - 21 Nov, 2013 - Comments: 0

Time to market and rising complexity are forcing the use of more third-party IP as well as increasing reuse of internally developed IP. But as more IP is added into SoCs, chipmakers are discovering some interesting things: Not all IP works together as planned, even when it’s well characterized. As with cars, performance and mileage vary greatly depending upon who’s driving—and who’s... » read more

HDMI 2.0 Design And Verification Challenges
By Various Writers - 21 Nov, 2013 - Comments: 0

HDMI designs face challenges with respect to run time and memory consumption due to the huge size of HDMI frames. Scrambling adds more complexity and designs face synchronization and timing challenges. Similar challenges are faced during the functional verification of systems-on- chip (SoCs) including HDMI interfaces. These challenges can be addressed using HDMI verification IP (VIP). To dow... » read more

Stacked Die Moves From Drawing Board To Reality
By Ed Sperling - 21 Nov, 2013 - Comments: 0

After decades of moving in a straight line from one process geometry shrink to the next, much of the semiconductor industry has taken a step back to figure out what comes next. While companies such as Intel, IBM and Samsung continue to look as far ahead as the 3nm process node, along with new materials to improve electron mobility and new transistor designs based on electron tunneling and carbo... » read more

The Hunt For The Next Application To Drive System-Level Design And Verification
By Frank Schirrmeister - 20 Nov, 2013 - Comments: 0

In recent years, most of my customer presentations highlighted some type of mobile device – system and system on chip (SoC) — to explain the challenges for system-level design and verification. But I also like to look into other application domains to understand how challenges may develop over time and to identify similarities and differences in challenges between application domains. Co... » read more

Blog Review: Nov. 20
By Ed Sperling - 20 Nov, 2013 - Comments: 0

Can you really heat your home office with just four candles? It all depends on where you put those candles, as Mentor’s Robin Bornoff shows in part one of this series. And make sure you check out the video, particularly if you’ve had a tough day. Synopsys’ Karen Bartleson interviews ST’s Oleg Logvinov on camera about the IoT, which may be the biggest change since the Industrial Revol... » read more

Experts At The Table: What’s Missing In The IoT
By Ed Sperling - 15 Nov, 2013 - Comments: 0

Semiconductor Engineering sat down to discuss the future of the IoT with Oleg Logvinov, director of market development for STMicroelectronics’ Industrial and Power Conversion Division; Martin Lund, senior vice president of the IP Group at Cadence; Naveed Sherwani, president and CEO of Open-Silicon; and Damon Hernandez, a member of the Web3D Consortium. What follows are excerpts of that conver... » read more

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