tag: Cadence

The Week in Review: System-Level Design
By Ed Sperling - 15 Nov, 2013 - Comments: 0

Cadence unveiled its next-gen power signoff tool, this one based upon parallel execution across multiple processors. The result is 10x speed improvement, according to the company. The signoff solution already is certified for TSMC’s 16nm finFET process for IR drop analysis and EM rule compliance, two of the big concerns with finFETs. Synopsys teamed up with CEVA to improve PPA for CEVA’s... » read more

IP Ecosystem Solutions For Complex Systems
By Joanne Itow - 14 Nov, 2013 - Comments: 0

At the Semico Impact Conference: Focus on the IP Ecosystem, Mahesh Tirupattur, Executive Vice President, Analog Bits, challenged four panelists to an engaging discussion on their approach to IP Ecosystem Solutions for Complex Systems. Panel participants included Dan Kochpatcharin, Deputy Director, IP Portfolio Management, TSMC; Jason Polychronopoulos, Mentor Graphics; Chris Rowen, Cadence Fello... » read more

From DFM To IFM
By Ed Sperling - 14 Nov, 2013 - Comments: 0

For the past decade the bridge between design and manufacturing was called, appropriately enough, design for manufacturing. DFM tools, which by nature cross boundaries of what previously were discrete segments in the semiconductor flow, are now critical for complex designs. They allow design teams to check early in the design process whether chips will yield sufficiently and to incorporate rule... » read more

Crunch Time
By Brian Fuller - 14 Nov, 2013 - Comments: 0

The electronics industry finds itself today at a tipping point (well, okay, another tipping point). Consider:  The network as we’ve known it for a couple of generations is changing before our eyes, not the least of which to accommodate the expected explosion of Internet of Things in the coming years. ARM CEO Simon Segars put it this way at the recent ARM TechCon event in Santa Clara: ... » read more

Blog Review: Nov. 13
By Ed Sperling - 13 Nov, 2013 - Comments: 0

Synopsys’ Brent Gregory digs into optimal paths—in this case between the bakery, the library and another store. This is the classic traveling salesman equation, but with a large sales staff and lots of stops. Mentor’s Michael Ford points to the gap between supply-chain and shop-floor management solutions. This is yet another example of thinking outside the package—and maybe the enti... » read more

Experts At The Table: The Future Of Verification
By Ed Sperling - 11 Nov, 2013 - Comments: 0

Semiconductor Engineering sat down to discuss the future of verification with Janick Bergeron, Synopsys fellow; Harry Foster, chief verification scientist at Mentor Graphics; Frank Schirrmeister, group director of product marketing for the Cadence System Development Suite; Prakash Narain, president and CEO of Real Intent; and Yunshan Zhu, vice president of new technologies at Atrenta. What foll... » read more

Low-Power Crisis = Danger & Opportunity
By Brian Fuller - 07 Nov, 2013 - Comments: 0

If you’re a student of these things, you’ve no doubt heard that in Japanese, the word “crisis” is divided equally into “danger” and opportunity.” The biggest opportunity for electronics designers is also their biggest challenge: power management. Ask anyone today and they’ll tell you that minding and managing power consumption and leakage is a big concern. How big? At DAC... » read more

Paving The Way To 16/14nm
By Ed Sperling - 07 Nov, 2013 - Comments: 0

The move to the next stop on the Moore’s Law road map isn’t getting any less expensive or easier, but it is becoming more predictable. Tools and programs are being expanded to address physical effects such as electrostatic discharge (ESD), electromigration and thermal effects from increased current density. Any or all of these three checklist items can affect the reliability of a chip. A... » read more

Atoms, ARMs, ARCs, Andes…And All The Rest
By Brian Bailey - 07 Nov, 2013 - Comments: 0

There was a time when nobody believed Intel processors would be replaced with any other device. Intel commanded the processor market. Rich Wawrzyniak, senior analyst for ASIC SoC at Semico Research, noted this was not always the case. In the early days of the PC there were many contenders and most people thought that Motorola would win because they had more money behind them. Ultimately, Intel ... » read more

The Problem With EDA Standards
By Brian Bailey - 07 Nov, 2013 - Comments: 0

In the EDA industry, does standard mean the same as it does in most industries? The Free Dictionary defines it as: Something, such as a practice or a product, that is widely recognized or employed, especially because of its excellence. In the EDA industry, a standards body is the place where EDA companies and customers come together to try and bring about convergence, often in a new or emerging... » read more

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