tag: Cadence

Experts At The Table: Stacking The Deck
By Ed Sperling - 26 Jul, 2012 - Comments: 0

By Ann Steffora Mutschler There is no doubt 3D stacking brings challenges not only from the design perspective, but also on the tool side. EDA vendors have been working for more than a few years to ready tools for stacked-die designs. How smooth the transition is, however, is a big question mark. Because the approach is new, not all the challenges are fully understood yet. And while most ED... » read more

Routing Congestion Returns
By Ed Sperling - 26 Jul, 2012 - Comments: 0

By Ed Sperling Routing congestion has returned with a vengeance to SoC design, fueled by the advent of more third-party IP, more memory, a variety of new features, as well as the inability to scale wires at the same rate as transistors. This is certainly not a foreign concept for IC design. The markets for place and route tools were driven largely by the need to automate this kind of operat... » read more

SoC Platforms Gain Steam
By Ed Sperling - 26 Jul, 2012 - Comments: 0

By Ed Sperling Platforms are attracting far more attention from makers of SoCs because they are pre-verified and can speed time to market, but the shift isn’t so simple. It will spark major changes in the way companies design and build chips, causing significant disruption across the entire SoC ecosystem. Platforms are nothing new in the processor and software world. Intel, IBM AMD, and N... » read more

Smarter Co-design With Models
By Ed Sperling - 26 Jul, 2012 - Comments: 0

By Ann Steffora Mutschler IC, package and PCB co-design methodologies are starting to be adopted by semiconductor companies. However, the existing die abstract file used in these flows to exchange data between the IC designer and the downstream package design team may not contain enough detail to drive advanced planning and optimization with the package and PCB interfaces. Engineering teams... » read more

Experts At The Table: Does 20nm Break System-Level Design?
By Ed Sperling - 26 Jul, 2012 - Comments: 0

By Ann Steffora Mutschler System-Level Design sat down to discuss design at 20nm with Drew Wingard, chief technology officer at Sonics; Kelvin Low, deputy director of product marketing at GlobalFoundries, Frank Schirrmeister, group director of product marketing for system development in the system and software realization group at Cadence; and Mike Gianfagna, vice president of marketing at At... » read more

Bringing Continuous Domain Into SystemVerilog Covergroups
By Various Writers - 26 Jul, 2012 - Comments: 0

This paper proposes a set of requirements for specifying functional coverage on an analog or mixed-signal block. We explain how the real number data type can be introduced in the [gettech id="31023" comment="SystemVerilog"] coverpoint specification and how it can enable a complete coverage specification for a mixed-signal verification environment. In discussing the requirements, we explore the... » read more

Increasing Certainty For 20nm Design
By Frank Schirrmeister - 25 Jul, 2012 - Comments: 0

By Frank Schirrmeister At the recent Design Automation Conference two topics were getting very special attention: Design at 20nm and System-Level Design. This is very indicative of the very opposite trends we have been facing in semiconductor designs for the last couple of decades. On the one hand, the actual design units get smaller and smaller, and we are today happily designing for technolo... » read more

Experts At The Table: Pain Points
By Ed Sperling - 20 Jul, 2012 - Comments: 0

By Ed Sperling Low-Power/High-Performance Engineering sat down with Vinod Kariat, a Cadence fellow; Premal Buch, vice president of software engineering at Altera; Vic Kulkarni, general manager of Apache Design; Bernard Murphy, CTO at Atrenta, and Laurent Moll, CTO at Arteris. What follows are excerpts of that conversation. LPHP: With stacked die it’s no longer one company making an SoC. W... » read more

Experts At The Table: Does 20nm Break System-Level Design?
By Ed Sperling - 13 Jul, 2012 - Comments: 1

By Ann Steffora Mutschler System-Level Design sat down to discuss design at 20nm with Drew Wingard, chief technology officer at Sonics; Kelvin Low, deputy director of product marketing at GlobalFoundries, Frank Schirrmeister, group director of product marketing for system development in the system and software realization group at Cadence; and Mike Gianfagna, vice president of marketing at Atr... » read more

Bridging The Rift Between Software And Hardware
By Ed Sperling - 12 Jul, 2012 - Comments: 0

By Ed Sperling As more computing is done on mobile devices rather than desktops, the idea of what constitutes good application software is changing. This addresses the key reason why some of advanced power-saving features built into chips were not utilized by software in the past. Unless the operating systems were specifically written for mobile devices, such as Android and iOS, the real f... » read more

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