tag: Cadence

Recipe To Catch Bugs Faster Using Machine Learning
By Anika Sunda - 19 Sep, 2022 - Comments: 0

We all agree that verification and debug take up a significant amount of time and are arguably the most challenging parts of chip development. Simulator performance has consistently topped the charts and is a critical component in the verification process. Still, the need of the hour is to stretch beyond simulator speed to achieve maximum verification throughput and efficiency. Artificial in... » read more

Week In Review: Auto, Security, Pervasive Computing
By Marie C. Baca - 16 Sep, 2022 - Comments: 0

Automotive and mobility U.S. President Joe Biden announced the approval of $900 million in funding for a nationwide network of electrical vehicle charging stations in 35 states. The money is part of a multi-year, $7.5 billion plan to create 500,000 charging stations along federal highways. Industry executives told Reuters that remote human supervisors may be a permanent fixture of highly au... » read more

Week In Review: Design, Low Power
By Jesse Allen - 16 Sep, 2022 - Comments: 0

Cadence unveiled a big data analytics infrastructure to unify massive data sets across all Cadence computational software. The Joint Enterprise Data and AI (JedAI) Platform aims to optimize multiple runs of multiple engines across an entire SoC design and verification flow. It combines data from its AI-driven Cerebrus implementation and Optimality system optimization solutions, along with the n... » read more

How Mature Are Verification Methodologies?
By Brian Bailey - 14 Sep, 2022 - Comments: 0

Semiconductor Engineering sat down to discuss differences between hardware and software verification and changes and challenges facing the chip industry, with Larry Lapides, vice president of sales for Imperas Software; Mike Thompson, director of engineering for the verification task group at OpenHW; Paul Graykowski, technical marketing manager for Arteris IP; Shantanu Ganguly, vice president o... » read more

Blog Review: Sept. 14
By Jesse Allen - 14 Sep, 2022 - Comments: 0

Synopsys' Godwin Maben, Piyush Sancheti, and Hany Elhak examine some of the top chip design considerations for medical devices and why they require careful analysis of power to reduce the number surgeries to replace batteries, reliability for devices that can be expected to last for ten years or more, and security to protect private medical data and prevent breaches. Siemens' Chris Spear exp... » read more

Designing For Thermal
By Karen Heyman - 13 Sep, 2022 - Comments: 0

Heat has emerged as a major concern for semiconductors in every form factor, from digital watches to data centers, and it is becoming more of a problem at advanced nodes and in advanced packages where that heat is especially difficult to dissipate. Temperatures at the base of finFETs and GAA FETs can differ from those at the top of the transistor structures. They also can vary depending on h... » read more

TSN-PTP: A Real-Time Network Clock Synchronizing Protocol
By Vedansh Seth - 13 Sep, 2022 - Comments: 0

In a network containing multiple nodes, the need for synchronization between the various nodes is not just instrumental but also a complicated and highly complex process. This process becomes even more tricky if we synchronize the clocks between the Manager and the Peripheral. As we know, in a real-time network, some of the nodes would behave like Managers while some would be a Peripheral. If w... » read more

New Data Management Challenges
By Ann Mutschler - 13 Sep, 2022 - Comments: 0

An explosion in semiconductor design and manufacturing data, and the expanding use of chips in safety-critical and mission-critical applications, is prompting chipmakers to collect and manage that data more effectively in order to improve overall performance and reliability. This collection of data reveals a number of challenges with no simple solutions. Data may be siloed and inconsistent, ... » read more

Preparation Of Geometry Models For Mesh Generation And CFD
By Cadence - 12 Sep, 2022 - Comments: 0

Making geometry models suitable for CFD meshing is a time-consuming bottleneck in CFD analysis. We will discuss why and ways to fix the problems. Click here to read more. » read more

Blog Review: Sept. 7
By Jesse Allen - 07 Sep, 2022 - Comments: 0

Cadence's Paul McLellan shares highlights from the recent Hot Chips tutorial on CXL and how enhanced memory pooling enables new memory usage models as CXL 3.0 approaches the same speed as DRAM. Synopsys' Sam Tennent and Kamal Desai highlight the emergence of virtual prototyping, its synergy with continuous integration and development setups, and the benefits when these disciplines are combin... » read more

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