Preparing For Test Early In The Design Flow


Until very recently, semiconductor design, verification, and test were separate domains. Those domains have since begun to merge, driven by rising demand for reliability, shorter market windows, and increasingly complex chip architectures. In the past, products were designed from a functional perspective, and designers were not concerned about what the physical implementation of the product ... » read more

Blog Review: March 2


Arm's Charlotte Christopherson checks out SpiNNaker1, a project to develop a massively parallel, manycore supercomputer architecture that mimicked the interactions of biological neurons, and its follow up, SpiNNaker2, a hybrid system that combines statistical AI and neuromorphic computing. Cadence's Paul McLellan looks at open and generic PDKs that can be used by researchers and in education... » read more

Week In Review: Design, Low Power


Tools & IP Codasip debuted two new customizable low power embedded RISC-V processor cores. To support embedded AI applications, the L31/L11 cores run Google’s TensorFlowLite for Microcontrollers. Codasip Studio tools can be used to customize for specific system, software, and application requirements. Licensing the CodAL description of a Codasip RISC-V core grants customers a full archit... » read more

Week In Review: Auto, Security, Pervasive Computing


Security Fraunhofer IIS received a grant to establish an R&D center for trustworthy integrated electronic systems for security and safety. Working with other Fraunhofer divisions, Fraunhofer IIS will use innovative methods in design and testing to help protect IP along the value chain of microelectronic components and systems. The center will focus on creating a secure design flow for inte... » read more

Data Center Architectures In Flux


Data center architectures are becoming increasingly customized and heterogeneous, shifting from processors made by a single vendor to a mix of processors and accelerators made by multiple vendors — including system companies' own design teams. Hyperscaler data centers have been migrating toward increasingly heterogeneous architectures for the past half decade or so, spurred by the rising c... » read more

Unintended Coupling Issues Grow


The number of indirect and often unexpected ways in which one design element may be affected by another is growing, making it more difficult to ensure a chip — or multiple chips in a package — will perform reliably. Long gone are the days when the only way that one part of a circuit could influence another was by an intended wire connecting them. As geometries get smaller, frequencies go... » read more

Are Sustainability And Safety Gen Z’s Top Requirements In 2031?


This blog is my 125th on the "Frankly Speaking" channel on SemiEngineering. A big thanks to Ed and his team for a great run and for putting up with my musings! I had started work-related blogging back in 2008, more company-specific, and some of these have since then vanished from the internet. Who would have thought! For this anniversary, I am looking forward ten years to 2031 and how generatio... » read more

RF To mmWave Design For Systems


RF-enabled next-generation communication systems and connected devices are differentiated by their performance, size, and cost. Traditionally, custom proprietary IC designs, leveraging the latest advanced-node technology, were developed to meet these product requirements. Increasingly these challenges are being met by moving beyond single IC solutions. Today’s electronic systems often integra... » read more

Blog Review: Feb. 23


Synopsys' Varun Agrawal looks at four new technologies have emerged to support the demands on 5G networks and applications, the challenges in validating all of those technologies together, and what's needed to perform end-to-end testing effectively for 5G O-RAN SoCs. Siemens EDA's Ray Salemi points to how FPGA retargeting could help address supply chain difficulties and some of the challenge... » read more

Week In Review: Design, Low Power


AMD completed its acquisition of Xilinx. The all-stock deal ended up being valued at approximately $50 billion due to a rise in AMD's share price (the deal was valued at $35 billion when announced). The Xilinx business will become the newly formed Adaptive and Embedded Computing Group (AECG), led by former Xilinx CEO Victor Peng, and will continue its FPGA, adaptive SoC, and software roadmaps a... » read more

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