tag: Carnegie Mellon University

Reducing The Cost of Cache Coherence By Integrating HW Coherence Protocol Directly With The Programming Language
By Technical Paper Link - 19 Mar, 2023 - Comments: 0

A new technical paper titled "WARDen: Specializing Cache Coherence for High-Level Parallel Languages" was published by researchers at Northwestern University and Carnegie Mellon University. Abstract: "High-level parallel languages (HLPLs) make it easier to write correct parallel programs. Disciplined memory usage in these languages enables new optimizations for hardware bottlenecks, such ... » read more

FPGA-based Infrastructure, With RISC-V Prototype, to Enable Implementation & Evaluation of Cross-Layer Techniques in Real HW (Best Paper Award)
By Technical Paper Link - 15 Mar, 2023 - Comments: 0

A technical paper titled "MetaSys: A Practical Open-Source Metadata Management System to Implement and Evaluate Cross-Layer Optimizations" was published by researchers at University of Toronto, ETH Zurich, and Carnegie Mellon University. This paper won the Best Paper Award at the HiPEAC 2023 conference. Abstract: "This paper introduces the first open-source FPGA-based infrastructure, MetaSy... » read more

Week In Review: Semiconductor Manufacturing & Test
By Gregory Haley - 17 Feb, 2023 - Comments: 0

The Biden Administration’s export bans for semiconductor manufacturing equipment are delaying expansion plans for Chinese chipmakers, Nikkei Asia reports. Yangtze Memory Technologies (YMTC) has halted work on its second memory plant near Wuhan, and ChangXin Memory Technologies (CMTX) says its second production facility, slated to open in 2023, will be delayed until 2024 or 2025. In an effo... » read more

Technical Paper Roundup: Sept. 12
By Linda Christensen - 12 Sep, 2022 - Comments: 0

New technical papers added to Semiconductor Engineering’s library this week. [table id=51 /] Semiconductor Engineering is in the process of building this library of research papers. Please send suggestions (via comments section below) for what else you’d like us to incorporate. If you have research papers you are trying to promote, we will review them to see if they are a good fit f... » read more

Mass Production of Soft And Stretchable Electronics
By Technical Paper Link - 07 Sep, 2022 - Comments: 0

This new technical paper titled "Scalable Manufacturing of Liquid Metal Circuits" was published by researchers at Carnegie Mellon University. The work presents "a novel technique for scalable and reproducible manufacturing of LM-based SSEs [soft and stretchable electronics] with integrated solid-state microelectronic components. The manufacturing technique is based on a selective metal-alloy... » read more

Technical Paper Round-up: June 14
By Linda Christensen - 14 Jun, 2022 - Comments: 0

New technical papers added to Semiconductor Engineering’s library this week. [table id=33 /] Semiconductor Engineering is in the process of building this library of research papers. Please send suggestions (via comments section below) for what else you’d like us to incorporate. If you have research papers you are trying to promote, we will review them to see if they are a good fit f... » read more

Deep Learning Applications For Material Sciences: Methods, Recent Developments
By Technical Paper Link - 10 Jun, 2022 - Comments: 0

New technical paper titled "Recent advances and applications of deep learning methods in materials science" from researchers at NIST, UCSD, Lawrence Berkeley National Laboratory, Carnegie Mellon University, Northwestern University, and Columbia University. Abstract "Deep learning (DL) is one of the fastest-growing topics in materials data science, with rapidly emerging applications spanning... » read more

Startup Funding: May 2022
By Jesse Allen - 06 Jun, 2022 - Comments: 0

May was another strong month for China as it continues its push to build a native semiconductor ecosystem. Over half the month's total funding went to startups in the country. Over half the companies funded were from China as well, including two FPGA companies, three making CPUs, a GPU startup, and numerous networking and wireless chip companies. Two of those, in FPGAs and CPUs, raised rounds s... » read more

Planning EDA’s Next Steps
By Ed Sperling - 24 Mar, 2022 - Comments: 0

Anirudh Devgan, Cadence's new CEO, and the recipient of the Phil Kaufman Award in December, sat down with Semiconductor Engineering to talk about what's next in EDA, the underlying technology and business challenges and changes, and new markets that are unfolding for floor-planning, verification, CFD, and advanced packaging. SE: Where does EDA need to improve? Devgan: We have made it much... » read more

Improving DRAM Performance, Security, and Reliability by Understanding and Exploiting DRAM Timing Parameter Margins
By Technical Paper Link - 14 Nov, 2021 - Comments: 0

Abstract: "Characterization of real DRAM devices has enabled findings in DRAM device properties, which has led to proposals that significantly improve overall system performance by reducing DRAM access latency and power consumption. In addition to improving system performance, a deeper understanding of DRAM technology via characterization can also improve device reliability and security. The... » read more

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