The Next Incarnation Of EDA

By Brian Bailey - 25 Aug, 2022 - Comments: 0

The EDA industry has incrementally addressed issues as they arise in the design of electronic systems, but is there about to be a disruption? Academia is certainly seeing that as a possibility, but not all of them see it happening for the same reason. The academic community questioned the future of EDA at the recent Design Automation Conference. Rather than EDA as we know it going away, they... » read more

Week In Review: Design, Low Power

By Jesse Allen - 19 Aug, 2022 - Comments: 0

The U.S. Commerce Department's Bureau of Industry and Security (BIS) issued new export controls on EDA software aimed at designing gate-all-around FETs, which manufacturers plan to implement starting at 3nm (Samsung) and 2nm (Intel and TSMC). Specifically, the ruling controls export of software that is specially designed for implementing RTL to GDSII (or an equivalent standard) for GAA FET desi... » read more

New Uses For AI In Chips

By John Koon and Ed Sperling - 11 Aug, 2022 - Comments: 1

Artificial intelligence is being deployed across a number of new applications, from improving performance and reducing power in a wide range of end devices to spotting irregularities in data movement for security reasons. While most people are familiar with using machine learning and deep learning to distinguish between cats and dogs, emerging applications show how this capability can be use... » read more

Improving PPA In Complex Designs With AI

By John Koon - 14 Feb, 2022 - Comments: 0

The goal of chip design always has been to optimize power, performance, and area (PPA), but results can vary greatly even with the best tools and highly experienced engineering teams. Optimizing PPA involves a growing number of tradeoffs that can vary by application, by availability of IP and other components, as well as the familiarity of engineers with different tools and methodologies. Fo... » read more

Week In Review: Manufacturing, Test

By Mark LaPedus - 12 Nov, 2021 - Comments: 0

Chipmakers AMD has rolled out its new MI200 series products, the first exascale-class GPU accelerators. Using a fan-out bridge packaging technology, the MI200 series are designed for high-performance computing (HPC) and artificial intelligence (AI) applications. The MI200 series accelerators feature a multi-die GPU architecture with 128GB of HBM2e memory. Typically, the HBM2e memory stack a... » read more

Week In Review: Design, Low Power

By Jesse Allen - 27 Aug, 2021 - Comments: 0

The UK's Competition and Markets Authority is raising new challenges for Nvidia's proposed acquisition of Arm, suggesting in a new report that an in-depth Phase 2 investigation into the deal is warranted on competition grounds. Andrea Coscelli, chief executive of the CMA, said, “We’re concerned that Nvidia controlling Arm could create real problems for Nvidia's rivals by limiting their acce... » read more

Week In Review: Manufacturing, Test

By Mark LaPedus - 23 Jul, 2021 - Comments: 0

Chipmakers and OEMs The industry is still wondering if Intel will buy GlobalFoundries (GF). In the meantime, GF has announced a fab expansion plan in upstate New York. These plans include immediate investments at its existing Fab 8 facility as well as construction of a new fab on the same campus. That will double the capacity at the site. Intel has reported its second-quarter 2021 financial... » read more

Week In Review: Manufacturing, Test

By Mark LaPedus - 23 Apr, 2021 - Comments: 0

Chipmakers and OEMs Several foundry vendors are building new fabs. The memory vendors, such as Samsung and SK Hynix, are also building new capacity. In another example, Taiwan DRAM supplier Nanya Technology plans to construct a new 300mm fab in the Taishan Nanlin Technology Park in New Taipei City. The plant will produce DRAMs with Nanya’s in-house developed 10nm-class process technologies a... » read more

Chiplet Reliability Challenges Ahead

By Ed Sperling - 12 Aug, 2020 - Comments: 2

Assembling chips using LEGO-like hard IP is finally beginning to take root, more than two decades after it was first proposed, holding the promise of faster time to market with predictable results and higher yield. But as these systems of chips begin showing up in mission-critical and safety-critical applications, ensuring reliability is proving to be stubbornly difficult. The main driver fo... » read more

The Next Advanced Packages

By Mark LaPedus - 18 Jun, 2020 - Comments: 4

Packaging houses are readying their next-generation advanced IC packages, paving the way toward new and innovative system-level chip designs. These packages include new versions of 2.5D/3D technologies, chiplets, fan-out and even wafer-scale packaging. A given package type may include several variations. For example, vendors are developing new fan-out packages using wafers and panels. One is... » read more

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Knowledge Centers
Entities, people and technologies explored

Shift Left Is The Tip Of The Iceberg

A transformative change is underway for semiconductor design and EDA. New languages, models, and abstractions will need to be created.

by Brian Bailey

Partitioning In The Chiplet Era

Understanding how chiplets interact under different workloads is critical to ensuring signal integrity and optimal performance in heterogeneous designs.

by Ann Mutschler

3.5D: The Great Compromise

Pros and cons of a middle-ground chiplet assembly that combines 2.5D and 3D-IC.

by Ed Sperling

AI’s Role In Chip Design Widens, Drawing In New Startups

Focus is on letting engineers do much more with the same or fewer resources — and less drudgery.

by Karen Heyman

Key Technologies To Extend EUV To 14 Angstroms

Alongside high-NA EUV will be better-performing photoresists, reduced roughness using passivation and etch, and lateral etching to reduce tip-to-tip dimensions.

by Laura Peters

Memory Fundamentals For Engineers

eBook: Nearly everything you need to know about memory, including detailed explanations of the different types of memory; how and where these are used today; what's changing, which memories are successful and which ones might be in the future; and the limitations of each memory type.

by The SE Staff

What Comes After HBM For Chiplets

The standard for high-bandwidth memory limits design freedom at many levels, but that is required for interoperability. What freedoms can be taken from other functions to make chiplets possible?

by Brian Bailey

Why Small Fab And Assembly Houses Are Thriving

Megafabs churning out the most advanced processors are not the only game in town.

by Bryon Moyer

tag: Cerebras

The Next Incarnation Of EDA

Week In Review: Design, Low Power

New Uses For AI In Chips

Improving PPA In Complex Designs With AI

Week In Review: Manufacturing, Test

Week In Review: Design, Low Power

Week In Review: Manufacturing, Test

Week In Review: Manufacturing, Test

Chiplet Reliability Challenges Ahead

The Next Advanced Packages