Precise Control Needed For Copper Plating And CMP

By Anne Meixner - 20 Jun, 2024 - Comments: 0

Chipmakers are relying on machine learning for electroplating and wafer cleaning at leading-edge process nodes, augmenting traditional fault detection/classification and statistical process control in order to extend the usefulness of copper interconnects. Copper is well understood and easy to work with, but it is running out of steam. At 5nm and below, copper plating tools are struggling to... » read more

TaN Nanowires At 300 mm Wafer Scale For Quantum Computing And More

By Technical Paper Link - 15 Jul, 2023 - Comments: 0

A technical paper titled "Ultra-thin TaN Damascene Nanowire Structures on 300 mm Si Wafers for Quantum Applications" was published by researchers at NY CREATES, United States Air Force Research Laboratory and SUNY Polytechnic Institute. Abstract: "We report on the development and characterization of superconducting damascene tantalum nitride (TaN) nanowires, 100 nm to 3 μm wide, with TaN thi... » read more

The Effect Of Pattern Loading On BEOL Yield And Reliability During Chemical Mechanical Planarization

By Taeyon (TY) Oh - 20 Jan, 2022 - Comments: 0

Chemical mechanical planarization (CMP) is required during semiconductor processing of many memory and logic devices. CMP is used to create planar surfaces and achieve uniform layer thickness during semiconductor manufacturing, and to optimize the device topology prior to the next processing step. Unfortunately, the surface of a semiconductor device is not uniform after CMP, due to different re... » read more

Reducing Rework In CMP: An Enhanced Machine Learning-Based Hybrid Metrology Approach

By Vamsi Velidandla - 10 Aug, 2021 - Comments: 0

By Vamsi Velidandla, John Hauck, Zhuo Chen, Joshua Frederick, and Zhihui Jiao The semiconductor industry is constantly marching toward thinner films and complex geometries with smaller dimensions, as well as newer materials. The number of chemical mechanical planarization (CMP) steps has increased and, with it, a greater need for within-wafer uniformity and wafer-to-wafer control of the thin... » read more

Inspection, Metrology Challenges Grow For SiC

By Mark LaPedus - 11 Jun, 2019 - Comments: 2

Inspection and metrology are becoming more critical in the silicon carbide (SiC) industry amid a pressing need to find problematic defects in current and future SiC devices. Finding defects always has been a challenging task for SiC devices. But it’s becoming more imperative to find killer defects and reduce them as SiC device vendors begin to expand their production for the next wave of a... » read more

Silicon Photonics: Solving Process Variation And Manufacturing Challenges

By Sandy Wen - 17 Aug, 2017 - Comments: 0

As silicon photonics manufacturing gains momentum with additional foundry and 300mm offerings, process variation issues are coming to light. Variability in silicon processing affects the waveguide shape and can result in deviation in effective indices, propagation loss, and coupling efficiency from the intended design. In this article, we will highlight process variation issues that can occur i... » read more

Increasing Challenges At Advanced Nodes

By Ed Sperling - 22 Oct, 2015 - Comments: 1

Gary Patton, chief technology officer at GlobalFoundries, sat down with Semiconductor Engineering to talk about new materials, stacked die, how far FD-SOI can be extended, and new directions for interconnects and transistors. What follows are excerpts of that conversation. SE: Where do you see problems at future nodes? Patton: At the device level, we have to be able to pattern these thing... » read more

Design Rules Explode At New Nodes

By Ed Sperling - 17 Nov, 2014 - Comments: 0

Semiconductor Engineering sat down changing design rules with Sergey Shumarayev, senior director of custom IP design at Altera; Luigi Capodieci, R&D fellow at [getentity id="22819" comment="GlobalFoundries"]; Michael White, director of product marketing for Calibre Physical Verification at [getentity id="22017" e_name="Mentor Graphics"], and Coby Zelnik, CEO of [getentity id="22478" e_name=... » read more

Front End Comes To The Back End

By Jeff Chappell - 19 Sep, 2013 - Comments: 0

By Jeff Chappell For outsourced assembly and test (OSAT) houses either planning for or already offering through-silicon via (TSV) capability for their 3D packaging efforts, this has meant the front end is coming to the back end, in a manner of speaking. A bit of an exaggeration perhaps, as most generalizations are. But thanks to TSVs, in a very real sense some of what would typically be the... » read more

Knowledge Centers
Entities, people and technologies explored

Shift Left Is The Tip Of The Iceberg

A transformative change is underway for semiconductor design and EDA. New languages, models, and abstractions will need to be created.

by Brian Bailey

Partitioning In The Chiplet Era

Understanding how chiplets interact under different workloads is critical to ensuring signal integrity and optimal performance in heterogeneous designs.

by Ann Mutschler

3.5D: The Great Compromise

Pros and cons of a middle-ground chiplet assembly that combines 2.5D and 3D-IC.

by Ed Sperling

AI’s Role In Chip Design Widens, Drawing In New Startups

Focus is on letting engineers do much more with the same or fewer resources — and less drudgery.

by Karen Heyman

Key Technologies To Extend EUV To 14 Angstroms

Alongside high-NA EUV will be better-performing photoresists, reduced roughness using passivation and etch, and lateral etching to reduce tip-to-tip dimensions.

by Laura Peters

What Comes After HBM For Chiplets

The standard for high-bandwidth memory limits design freedom at many levels, but that is required for interoperability. What freedoms can be taken from other functions to make chiplets possible?

by Brian Bailey

Memory Fundamentals For Engineers

eBook: Nearly everything you need to know about memory, including detailed explanations of the different types of memory; how and where these are used today; what's changing, which memories are successful and which ones might be in the future; and the limitations of each memory type.

by The SE Staff

Why Small Fab And Assembly Houses Are Thriving

Megafabs churning out the most advanced processors are not the only game in town.

by Bryon Moyer

tag: chemical mechanical planarization