tag: chip design news

Week In Review: Design, Low Power
By Jesse Allen - 04 Aug, 2023 - Comments: 0

Qualcomm, NXP, Infineon, Nordic, and Bosch are jointly investing in a new RISC-V company, to be formed in Germany, that will speed up RISC-V’s adoption in commercial products. The company will be “a single source to enable compatible RISC-V based products, provide reference architectures, and help establish solutions widely used in the industry,” according to a press release. The co... » read more

Week In Review: Design, Low Power
By Linda Christensen - 21 Apr, 2023 - Comments: 0

Cadence rolled out a slew of new products at this week’s CDNLive Silicon Valley, including: A new generative AI-powered tool for analog, mixed-signal, RF and photonics design; An extended collaboration with TSMC and Microsoft to advance giga-scale physical verification system in the cloud; A multi-year partnership with the San Francisco 49ers football organization, focused on sust... » read more

Week In Review: Design, Low Power
By Jesse Allen - 07 Apr, 2023 - Comments: 0

MLCommons debuted the latest results for the MLPerf Inference v3.0 and Mobile v3.0 benchmark suites, which measure the performance and power-efficiency of applying a trained machine learning model to new data in data center, edge, and mobile use cases. Overall, MLCommons said the results showed both power efficiency improvements and significant gains in performance in some benchmark tests. Seve... » read more

Week In Review: Design, Low Power
By Linda Christensen - 24 Mar, 2023 - Comments: 0

Renesas will acquire Panthronics, a fabless semiconductor company specializing in high-performance wireless products, expanding its reach into near-field communications for financial, IoT, asset tracking, wireless charging, and automotive applications. The two companies already had collaborated on designs for mobile point-of-sale terminals, wireless charging, and smart metering. Renesas also... » read more

Week In Review: Design, Low Power
By Linda Christensen - 17 Feb, 2023 - Comments: 0

It’s earnings season. Arm, Cadence, Synopsys, Siemens (consolidated), Rambus, and Renesas reported quarterly results over the past couple weeks. All posted year-over-year revenue growth, despite an overall challenging macroeconomic climate. A roundup of all the chip industry earnings reports from the past several weeks can be found here. The edge computing market is projected to jump to al... » read more

EDA, IP Growth Surges Again
By Ed Sperling - 24 Jan, 2023 - Comments: 0

EDA tools and IP revenue increased 8.9% in Q3 of 2022 to $3.767 billion, up from $3.458 billion in 2021, according to a just-released report from the ESD Alliance at SEMI. All regions except Japan reported growth, but the numbers were a bit more uneven in Q3 than in recent quarters. For example, total silicon IP dropped 1%, while services revenue grew 20.8%. At the same time, EDA revenue jum... » read more

Week In Review: Design, Low Power
By Jesse Allen - 13 Jan, 2023 - Comments: 0

With funding from the Semiconductor Research Corporation, a group of 10 universities is banding together to create the Processing with Intelligent Storage and Memory center, or PRISM, led by University of California San Diego. The $50.5 million PRISM center will focus on four different themes: novel memory and storage devices and circuits; next generation architectures; systems and software; an... » read more

Week In Review: Design, Low Power
By Marie C. Baca - 06 Jan, 2023 - Comments: 0

Top Of The News Google announced it will support the RISC-V architecture with the Android open-source operating system. In a keynote at the RISC-V Summit, Lars Bergstrom, Google's director of engineering for the Android Platform Programming Languages, noted that Android currently has more than 3 billion users and the support of more than 24,000 vendors. "We've been following RISC-V for a very ... » read more

Week In Review: Design, Low Power
By Marie C. Baca - 02 Dec, 2022 - Comments: 0

Tools and IP Renesas released a family of configurable clock generators with an internal crystal oscillator for PCIe and networking applications in high-end computing, wired infrastructure and data center equipment. “Timing needs can vary greatly between different applications and equipment, and often change during a product design cycle,” said Zaher Baidas, Vice President of the Timing Pr... » read more

Week In Review: Design, Low Power
By Jesse Allen - 11 Nov, 2022 - Comments: 0

Chip design Fraunhofer IIS/EAS implemented the Bunch of Wires (BoW) standard-based interface IP from the Open Compute Project (OCP) on Samsung's 5nm technology. The effort is intended to make chiplets more feasible for products with small and medium-sized production runs and determine the need for additional uniform standards in the future, such as for die-to-die bonding. “As part of t... » read more

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