tag: chip design

From AI Algorithm To Implementation
By Brian Bailey - 10 Apr, 2019 - Comments: 0

Semiconductor Engineering sat down to discuss the role that EDA has in automating artificial intelligence and machine learning with Doug Letcher, president and CEO of Metrics; Daniel Hansson, CEO of Verifyter; Harry Foster, chief scientist verification for Mentor, a Siemens Business; Larry Melling, product management director for Cadence; Manish Pandey, Synopsys fellow; and Raik Brinkmann, CEO ... » read more

Blog Review: April 3
By Jesse Allen - 03 Apr, 2019 - Comments: 0

Synopsys' Taylor Armerding contends that as the IoT becomes more ubiquitous, the threat of cyber-physical attacks is rising, with the potential for a domino effect if even simple devices are compromised in large enough quantities. Mentor's Colin Walls considers the move away from programming on bare metal with the rise of drivers and RTOSes and when it makes sense to still use the old method... » read more

Heterogeneous Design Creating Havoc With Firmware Versions
By Ed Sperling - 01 Apr, 2019 - Comments: 0

Adding different kinds of processing elements into chips is creating system-level incompatibilities because of sometimes necessary, but usually uncoordinated, firmware updates from multiple vendors. In the past, firmware typically was synchronized with other firmware and the chip was verified and debugged. But this becomes much more difficult when multiple heterogeneous processing elements a... » read more

Week In Review: Design, Low Power
By Jesse Allen - 22 Mar, 2019 - Comments: 0

Synopsys announced several new products: a new test family, a physical verification solution, and a software library for neural net SoCs. TestMAX, the new family of test products, includes soft error analysis and X-tolerant logic BIST for automotive test and functional safety requirements. TestMAX enables test through functional high-speed interfaces and supports early validation of DFT logi... » read more

The Growing Challenge Of Thermal Guard-Banding
By Ann Mutschler - 18 Mar, 2019 - Comments: 1

Guard-banding for heat is becoming more difficult as chips are used across a variety of new and existing applications, forcing chipmakers to architect their way through increasingly complex interactions. Chips are designed to operate at certain temperatures, and it is common practice to develop designs with some margin to ensure correct functionality and performance throughout the operat... » read more

Week In Review: Design, Low Power
By Jesse Allen - 08 Mar, 2019 - Comments: 0

Cadence debuted Denali Gen2 IP for LPDDR5/4/4X in TSMC's 7nm FinFET process technology. The offering consists of PHY, controller and Verification IP. It supports both the pre-release LPDDR5 standard and LPDDR4/4X devices as well as Arm AMBA AXI buses and reliability features like in-line error correcting codes. The LPDDR5 standard provides up to 1.5x bandwidth over LPDDR4 and LPDDR4X. The US... » read more

New Design Approaches At 7/5nm
By Ed Sperling - 04 Mar, 2019 - Comments: 0

The race to build chips with a multitude of different processing elements and memories is making it more difficult to design, verify and test these devices, particularly when AI and leading-edge manufacturing processes are involved. There are two fundamental problems. First, there are much tighter tolerances for all of the components in those designs due to proximity effects. Second, as a re... » read more

Week In Review: Design, Low Power
By Jesse Allen - 01 Mar, 2019 - Comments: 0

Tools & IP OneSpin Solutions debuted the Hardware Metric Calculation (HMC) App, which uses automatically extracted design information to calculate key hardware metrics to comply with functional safety standards. In particular, it focuses on automotive and autonomous driving SoCs needing to meet the highest functional safety requirements defined by the ISO 26262 standard. The HMC App calcul... » read more

Week in Review: Design, Low Power
By Susan Rambo - 08 Feb, 2019 - Comments: 0

The U.S. Department of Energy (DOE) has awarded $35 million for 12 projects involving ultra-efficient power management. Called Arpa-E, the program encouraged participants to use medium-voltage electricity in new ways with real-world applications, such as industry, transportation and the grid. The top two award winners were Eaton Corp. (Arden, NC) for its DC wide-bandgap static circuit breaker, ... » read more

The Data Deluge
By Ed Sperling - 23 Jan, 2019 - Comments: 0

Lip-Bu Tan, president and CEO of Cadence, sat down with Semiconductor Engineering to discuss the intersection of big data and technology, from the data center to the edge and vertical markets such as automotive. What follows are excerpts of that conversation. SE: What are the biggest changes you've seen over the past year? Tan: We are moving quickly toward data-driven economics. There... » read more

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