Week In Review: Design, Low Power

Synopsys’ new test products, ML library; Vayyar licenses Arteris IP’s interconnect.


Synopsys announced several new products: a new test family, a physical verification solution, and a software library for neural net SoCs.

TestMAX, the new family of test products, includes soft error analysis and X-tolerant logic BIST for automotive test and functional safety requirements. TestMAX enables test through functional high-speed interfaces and supports early validation of DFT logic through full RTL integration while maintaining physical-, timing-, and power-awareness through direct links into the company’s Fusion Design Platform. The tools also support early testability analysis and planning, hierarchical ATPG compression, physically-aware diagnosis, logic BIST, memory self-test and repair, and analog fault simulation.

Synopsys’ latest physical verification solution, IC Validator NXT, has a massively parallel distributed processing architecture and is scalable to 2000+ CPUs, which the company says speeds physical signoff cycle by 2X for advanced technology nodes. New DRC technology offers 5X faster runtime with 5X fewer CPUs and order-of-magnitude debugging speed-up. It also includes LVS, PERC, dummy metal fill, and DFM enhancement capabilities.

Finally, the embARC Machine Learning Inference software library aims to facilitate development of power-efficient neural network SoC designs incorporating DesignWare ARC EMxD and HS4XD DSP Processor IP. The software library provides optimized functions to implement neural network layer types, reducing processor cycle counts for low-power IoT applications. It provides a set of essential kernels for effective inference of small- or mid-sized machine learning models and enables the efficient implementation of operations such as convolutions, long short-term memory (LSTM) cells, pooling, activation functions such as rectified linear units (ReLU), and data routing operations, including padding, transposing, and concatenation, while reducing power and memory footprint.

Vayyar Imaging licensed Arteris IP’s FlexNoC interconnect IP and the accompanying FlexNoC Resilience Package for use in its next-generation RF 3D imaging chips for automotive systems. Vayyar’s current generation of chips covers multiple radar bands from 3 to 81 GHz and implements 72 transmitters and 72 receivers along with an integral advanced DSP. Vayyar cited the inclusion of data protection mechanisms that increase functional safety to meet automotive standards as part of the decision.

Samsung announced development of a 3rd-generation 10nm -class (1z-nm) 8Gb DDR4 DRAM without the use of EUV. The company reports more than 20% higher manufacturing productivity compared to the previous 1y-nm version. Mass production will begin within the second half of this year.


DATE 2019: Mar. 25-29 in Florence, Italy. The conference and exhibition will feature keynotes on heterogeneous computing in cloud and HPC as well as the limitations of modeling frameworks for intelligent systems. Sessions will highlight emerging design technologies, design and test of secure systems, embedded systems for deep learning, and more.

Linley Spring Processor Conference 2019: April 10-11 in Santa Clara, CA. Beginning with an overview of the processor and IP market, technologies, equipment-design, and silicon trends, the event will include talks and panel discussions on a range of topics. AI chips and IoT security are both major focuses.

DAC 2019: June 2-6 in Las Vegas, NV. The conference and exhibition includes a range of tracks, including last year’s addition of machine learning/AI. On the show floor, the Design Infrastructure Alley will return for a second year. Free registration is now open to attend the exhibits and keynotes, sponsored by Avatar Integrated Systems, ClioSoft and Truechip.

ES Design West: July 9-11 in San Francisco, CA. The new conference focuses on IP, EDA, embedded software, design services, and infrastructure. Along with a dedicated conference track, there will be presentations and panels on the show floor. Presented by the ESD Alliance, the conference is co-located with SEMICON West. Super-early registration ends Mar. 29.

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